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2SC48634 Datasheet
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2SC48634 Price

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2SC48634 on stock
To provide the merge and collapse features, the write buffer incorporates a content-addressable memory (CAM). The CAM performs a look-up of DWORD addresses that currently exist within the write buffer with an address presented by the Am5x86 CPU, PCI host bridge, or GP bus DMA that requests the write transfer. During a CPU or PCI host bridge burst transfer, each DWORD address during the transfer is searched within the CAM.

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0 ±400 mA Rated Current (3) MIN MAX +1100/-900 +500 4.95
11.90 12.00 12.1 0 14.90 15.00 15.10 VDC Voltage Range 100% Load MIN TYP MAX 5.00 5.05 O6
% Output Balance (Plus to Minus Output, Full Load) TYP MAX 1.0 O05
0.02 0.07 Load0.02ulation 0-100% Load % 0.07 TYP MAX 0.10 0.02
% Line Regulation Vin = Min-Max VDC TYP MAX 0.07 O02
% Short Term Stability (4) TYP 0.3
%/kHrs Long Term Stability TYP 20
LtSec Transient Response (5) TYP 20
mV peak Dynamic Response (6) TYP 60
cIB Input Ripple Rejection (7) TYP 10
mV p-p Noise, 0-20MHz BW TYP MAX 40 100
50 150 Temp50ature Coefficient 150 ppm/oC TYP MAX 300
Short Circuit Protection to Common for all Outputs Continuous, 8 Hours Minimum Current Limit NOTES
Application Notes for the definition of terms, measurement circuits and other information. (1) All parameters measured at 250C, nominal input vottage and full rated load unless otherwise noted. Refer to the Calex