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4040LN103Z5 Datasheet

Peak Collector Current (Tj " 150YC) ICM 600* Amperes Emitter Current" (Tc = 25YC) IE 300 Amperes
4040LN103Z5 Price

D (DEC)	RWA (Q)	Output State
127 64 1 0	74 5035 9996 10035	F ull-S cale Midscale (RS = 0 Condition) 1 LSB Zero-Scale

4040LN103Z5 on stock

In order to avoid any system failure, a sequence of several conditions has to be passed. In case of Vcc power down ( Vcc< VRT for t > tRR) a logic LOW signal is generated at the pin RO to reset an external microcontroller. When the level of Vcc reaches the reset threshold VRT, the signal at RO remains LOW for the Power-up reset delay time tRD before switching to HIGH. If Vcc drops below the reset threshold VRT for a time extending the reset reaction time tRR, the reset circuit is activated and a power down sequence of period tRD iS initiated. The reset reaction time tRR avoids wrong triggering caused by short "glitches" on the Vcc-Iine.

(VDS	= 5V, f	= 900}	rlHz)
		-		VG2S=	- 1.5V
				j	1.OV
					0.5V

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