BL-B3130A Price MAG 0.013 0.024 0.035 0.044 0.053 0.059 0.064 0.068 0.071 0.075 0.078 0.080 0.081 0.082 0.082 0.084 0.086 0.086 0.087 0.088 0.088 0.089 0.088 0.088 0.088 0.086 0.086 0.086 0.086 0.086 BL-B3130A on stock| SYMBOL | PARAMETER | MAX | UNIT | | VDS ID Ptot T. RDScON) | Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature D rain-source on-state resistance Vls = 5V Vls = 7V | 50 15 40 150 125 100 | V A W C l | | SYMBOL | PARAMETER | NOM | UNIT | | VPSN | Protection supply voltage BUK104-50L BUK104-50S | 5 1 0 | V V | | | | |
| Symbol | Parameter | Test Condition | Min | Typ | Max | Unit | | ti ,LI-LO ti ,KI- RX tr,TX-KO/SDL tr,TX-KO/ISO | Rise Time | for the definition of ti, t2 see fig 2 for SDL: VDiag = Vs-r = 5v Vz = 12V Tj 250C, (1) | 10 | 1.5 1.5 15 3 | 20 5O | US US US US | | t2 ,11-10 t2 ,KI- RX tr,TX-KO/SDL tr,TX-KO/ISO | Fall Time | for ISO: VDiag = Vz = 12V | 1 0 | 1.5 1.5 15 3 | 20 5O | US US US US | | Vext KO | External KO Negative Clamp Voltage | RLKO = 75Q; VKO > VKO sub-diode @IKO = -100yA, Vz = OV; tj = 250C | 1.5 | | | V | | Inverter Matrix/ Static Input Signal | | VIN1 2L | Input Voltage Low | | -0.15 | | 1 | V | | VINl, 2H | Input Voltaqe Hiqh | | 2 | | VST-r0.15 | V | | RIN1 2 | Input Resistor at INl, IN2 Input | -0.15 < VINl,2 < VST+0.15V | 14 | 20 | 36 | KQ | | Current Consumption | | IST | Supply Current | Vs-r .< 5.25V; C11,2,3,Tx, Ki = (LOW) INl,IN2= (LOW) OV < VPl,2 < VST | | | 6 | mA | | lz | Supply Current | vz16V | | | 1 0 | mA | | IDiag | Supply Current | 4.75V < VDiag < 16V | | | 4 | mA | | VCCR | Reverse Supply | Rexti 10MQ @ Vcc allinputs open VZ= VDiaa = 4.3V | | | 0 2 | V | | Diode (only on chip available) | | VCL | Clamping Voltage | IF, = 10mA, Tj = 250C | | | 1 0 | V | | TK | Clamping Voltage Temp. Coefficient | | -25 | | 1O | mV/K | | VBR | Reverse Breakdown Voltage | IR = 1 00LiA; Tj = 1250C | 50 | | | V | | VBRSub | Substrate Breakdown Voltage | ISub = 10011A; Tj = 1250C | 50 | | | V | | | | | | | |
For dc coupled analog input applications, amplifier U2 is con- figured to operate as a unity gain inverter with adjustable offset for the analog input signal. For full-scale AD C drive the analog input signal should be l V p-p int0 50 I (Rl) referenced to ground (0 V). The amplifier offsets the analog signal by +VREF (+2.5 V typical) to center the voltage for proper ADC input drive. For dc coupled operation, connect El to E2 (ana- log input to R2) and Ell to E12 (amplifier output to analog input ofAD 9057) using the board jumper connectors. DC offset ofthe analog input signal can be modified by adjusting potentiometer Rl0.
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