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There is a master power-down signal (MS_PWDN) to put the entire device into a low power consumption state. In addi- tion, there is a power-down control signal for each of the eight channels. This allows the device to efficiently operate as one to eight 10-bit serializers. The @SPEED TEST signal initiates the sending of a random data pattern over the LVDS links. This allows for testing the links for bit error rates at the frequency they will be carrying data. In addition, JTAG can be used to verify the device interconnects and initiate/verify the at-speed BIST. The SCAN928028 has four operating modes. They are the Initialization, Data Transfer, Resynchronization, @SPEED TEST states. There are also two passive states: Power- down and TRI-STATE. In addition to the active and passive states, there are test modes for JTAG access and at-speed BIST.
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