| | INCHES | MILLIMETERS |
| DIM | MIN | MAX | MIN | MAX |
| A | 0 235 | 0 245 | 5 97 | 6 22 |
| B | 0 250 | 0 265 | 6 35 | 6 73 |
| C | 0 086 | 0 094 | 2 19 | 2 38 |
| D | 0 027 | 0 035 | 0 69 | 0 88 |
| E | 0 018 | 0 023 | 0 46 | 0 58 |
| F | 0 037 | 0 045 | 0 94 | 1 14 |
| G | 0.180 BSC | 4.58 BSC |
| H | 0 034 | 0 040 | 0 87 | 1 01 |
| J | 0 018 | 0 023 | 0 46 | 0 58 |
| K | 0 102 | 0 114 | 2 60 | 2 89 |
| L | 0.090 BSC | 2.29 BSC |
| R | 0 180 | 0 215 | 4 57 | 5 45 |
| S | 0 025 | 0 040 | 0 63 | 1 01 |
| U | 0 020 | | 0 51 | |
| V | 0 035 1 0 050 | 0 89 1 1 27 |
| Z | 0 155 | | 3 93 | |
| | | | |
NOTES: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP). 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop.
