TIMap-1241  > CY74FCT273CTSOC
description IC OCT D F-F 8BIT REG 20SOIC
Technical/Catalog Information CY74FCT273CTSOC
Vendor Texas Instruments
Category Integrated Circuits (ICs)
RoHS Status RoHS Compliant
Other Names CY74FCT273CTSOC CY74FCT273CTSOC
Lead Free Status Lead Free
Type D-Type Bus
Packaging Tube
Operating Temperature -40掳C ~ 85掳C
Package / Case 20-SOIC (7.5mm Width)
Mounting Type Surface Mount
Function Master Reset
Number of Elements 1 - Single
Number of Bits per Element 8
Output Type Non-Inverted
Supply Voltage 4.75 V ~ 5.25 V
Current - Output High, Low 颅32mA, 64mA
Trigger Type Positive Edge
Frequency - Clock -
Delay Time - Propagation 2ns

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CY74FCT273CTSOC Datasheet

Symbol Parameter Min Max Units Reference Test Method
NEND(3) ndurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
TDR(3) Data Retention 1 00 Years MIL-STD-883, Test Method 1008
VZAp(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(3)(4) Latch-up 1 00 mA JEDEC Standard 17


CY74FCT273CTSOC Price
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (T0220) envelopes. 3. Epoxy meets UL94 VO at l/8".
CY74FCT273CTSOC on stock
Protoco I Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure l). On power-up of the ISL95711 the SDA pin is in the input mode. AIII2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL95711 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure l). A START condition is ignored during the power-up sequence and during internal non-volatile write cycles. AIII2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure l). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. A STOP condition during a write operation to a non-volatile byte, initiates an internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed.
1) CPD isdefined as the value of the IC'sinternal equivdent cEpaatance which is calculated from the operating current consurrption without load. Average operting current can be obtained by the following equation. Icc(opr) = CPD . Vcc fIN +lco'16 (per circuit)
I Any and all SANYO products described or contained applications that require extremely high levels of re control systems, or other applications whose failure physical and/or material damage. Consult with your any SANYO products described or contained herein