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Notes: 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of l.5V, and output loading as shown in the AC Test Loads and Waveforms and capacitance as in Note 7, unless otherwise specified. 10. Access time includes all data outputs switching simultaneously. 11. tSKEWl iS the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes of flag update). If the opposite clock occurs less than tSKEWl after the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synch ronized; i.e., CKW is the opposite clock for Empty and Almost Empty flags, CKR is the opposite clock for the Almost Full flag. The clock is the signal to which a flag is synchronized; i.e., CKW is the clock for the Almost Full flag, CKR is the clock for Empty and Almost Empty flags. 12. tSKEW2 iS the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for purposes of flag update). If the opposite clock occurs less than tSKEW2 before the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. See Note 11 for definition of clock and opposite clock.