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of data presentation. A diagram illustrating this autodetection behavior is shown in Figure 2. At power-up, the inte rface is set to l-wire pulse mode. If the CS line ever goes low (as it will at the beginning of a valid 3-wire se rial transfer) the chipimmediately reconfigures itselfint0 3-wire mode and remainsin this mode until poweris cycled. If CS stays high,the device staysin pulse modeand monitorsthe U P/DN pin to determine whetherto switch t0 2-wire mode. If U P/DN ever goes low (as it will the first time a "down" command is given) the chip switches int0 2-wire pulse mode and remains in this mode until power is cycled. In a properly configured l-wire system, CS and UP/DN will always remain high. 2-wire pulse mode systems must provide a single logic low pulse before the first data pulses are sent to prevent the LTC1428-50 from remaining in l-wire mode if the first several pulses are logic high.