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Since no address setup time is required, data access is quite simple. With WE high and CS low, the array may be read by simply toggling the input address. Valid data output becomes available after time TA, following each address change. However, should CS be used to control the read mode, valid data access time must be equal to or greater than TA, but cannot occur earlier than Tco from CS going low. The write mode is enabled whenever CS and WE are both low. Stored data integrity is therefore preserved as long as either CS or WE is high. To write valid