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If the ADSP-216x is performing an external memory access when the external device asserts the BR signal, it will not three- state the memory interfaces or assert the B~ signal until the cycle after the access completes (up to eight cycles later depend- ing on the number of wait states). The instruction does not need to be completed when the bus is granted; the ADSP-21xx will grant the bus between two memory accesses if an instruction requires more than one external memory access.
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