| January 1990 PAIRCHILD Revised November 1999 SEMICONDUCTOF~Th/ 74ACQ573 . 74ACTQ573 Quiet SeriesTM Octal Latch with 3-STATE Outputs General Description Features The ACQ/ACTQ573 is a high-speed octal latch with buff- s ICC and loz reduced by 50% ered common Latch Enable (LE) and buffered common s Guaranteed simultaneous switching noise level and Output Enable (OE) inputs. The ACQ/ACTCl573 is func- tionally identical to the ACQ/ACT0373 but with inputs a cd dynamic threshold performance outputs on opposite sides of the package. The ACO/ACTQ s Guaranteed pin-to-pin skew AC performance utilizes Fairchild's Ouiet SeriesTM technology to guarantee s Improved latch-up immunity quiet output switching and improved dynamic threshold s Inputs and outputs on opposite sides of package allow performance. FACT Quiet SeriesTM features GTOTM output easy interface with microprocessors control and undershoot corrector in addition to a split s Outputssource/sink 24 mA ground bus for superior performance. Ordering Code: |
| Order Number | Package Number | Package Description |
| 74AC0573SC | M20B | 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body |
| 74AC0573SJ | M20D | 20-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide |
| 74AC0573MTC | MTC20 | 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC M0-153, 4.4mm Wide |
| 74ACQ573PC | N20A | 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-O01, 0.300" Wide |
| 74ACTQ573SC | M20B | 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-01 3, 0.300" Wide Body |
| 74ACTCl573SJ | M20D | 20-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide |
| 74ACT0573ClSC | MQA20 | 20-Lead Quarter Size Outline Package (QSOP), JEDEC M0-137, 0.150" Wide |
| 74ACTCl573PC | N20A | 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-O01, 0.300" Wide |
| Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Logic Symbols Connection Diagram |
| IEE E/IEC | 20 | -vce |
| OE _b LE - DO Dl D2 D3 | IEN1 | DO - Dl- 02 - D3 - Jo D4 - Jl D5 - J2 D6- D7 - J3 GND- | 19 18 4 17 16 15 14 13 12 10 11 | -oo -Ol -02 -03 -04 -05 -06 -07 -LE |
| D4 D5 D6 D7 | | Js Pin Descriptions J7 Pin Names Description |
| I IIIIII I | DO-D7 | Data Inputs | |
| DO Dl D2 D3 D4 D5 06 D7 LE OE O0 01 02 03 04 05 06 07 | | LE OE 00-07 | Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs |
| IIIIIIII FACTn^. Quiet Series . FACT Quiet Seriesm. and GTOTM are trademarks of Fairchild Semiconductor Corporation |
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