The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con- tent occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.
MBA0204501CT150R Price Absolute Maximum Ratings at Ta= 250C Drain to Source Voltage VDSS Gate to Source Voltage VGSS Drain Current (DC) ID Drain Current (Pulse) lDP PW 10ps, duty cycle 1% Allowable Power Dissipation PD ChannelTemperature Tch Storage Temperature Tstg
MBA0204501CT150R on stock| Supply voltage (pin 11) | Vp | typ | 12 | V |
| Supply current | IP | typ | 13,5 | mA |
| I.F. voltage gain at f = 5,5 MHz | Gv if | typ | 68 | dB |
| Input voltage starting limiting | Vi | typ | 30 | ccV |
| AM suppression at Cf = +50 kHz | | typ | 60 | dB |
| A.F. output voltage adjustment range (pin 8) | O\/o af | typ. | 85 | dB |
| A.F. output voltage at Cf = + 50 KHz (r.m.s. value) |
| at pin 8 | Vo af (rms) | typ | 1,2 | V |
| at pin 12 | Vo af (rms) | typ | 1,0 | V |
| | | | |
| | | 70 ns | |
| Parameter | Description | Min | Max | Unit |
| Read Cycle |
| tRC | Read Cycle Time | 70 | | ns |
| tAA | Address to Data Valid | | 70 | ns |
| tOHA | Data Hold from Address Change | 10 | | ns |
| tACE | CE LOW to Data Valid | | 70 | ns |
| tDOE | OE LOW to Data Valid | | 25 | ns |
| tLZOE | OE LOW to Low-2[7, 9l | 5 | | ns |
| tHZOE | OE HIGH to High-2[9] | | 20 | ns |
| tLZCE | CE LOW to Low-2[7] | 10 | | ns |
| tHZCE | CE HIGH to High-Z[' 9] | | 20 | ns |
| tPU | CE LOW to Power-up | 0 | | ns |
| tPD | CE HIGH to Power-down | | 70 | ns |
| tDBE | BHE / BLE LOW to Data Valid | | 70 | ns |
| tLZBE[8] | BHE/ BLE LOW to Low-Z | 5 | | ns |
| tHZBE | BHE/ BLE HIGH to High-Z | | 20 | ns |
| Write Cycle['0. 11] |
| twc | Write Cycle Time | 70 | | ns |
| tSCE | CE LOW to Write End | 60 | | ns |
| tAW | Address Set-up to Write End | 60 | | ns |
| tHA | Address Hold from Write End | 0 | | ns |
| tSA | Address Set-up to Write Start | 0 | | ns |
| tPWE | WE Pulse Width | 40 | | ns |
| tBW | BHE / BLE Pulse Width | 60 | | ns |
| tSD | Data Set-up to Write End | 30 | | ns |
| tHD | Data Hold from Write End | 0 | | ns |
| oHZWE | WE LOW to High-Z[' 9] | | 25 | ns |
| tLZWE | WE HIGH to Low-2[7] | 10 | | ns |
| | | | |
