| | |
| | | DIMENSIONS |
| El | REF | Mimeters | Inches |
| | | | Min | Max | Min | Max |
| | | | | |
| | | | Al | 1.90 | 2.03 | 0.075 | 0.080 |
| | _________ | D | A2 | 0.05 | 0.20 | 0.002 | 0.008 |
| F | b | 1.25 | 1.65 | 0.049 | 0.065 |
| | | | C | 0.15 | 0.41 | 0.006 | 0.016 |
| | 7 | | | | d b | | E | 4.80 | 5.60 | 0.189 | 0.220 | |
| | | g L |
| 9 | El | 3.95 | 4.60 | 0.156 | 0.181 | |
| D | 2.25 | 2.95 | 0.089 | 0.116 | |
| L | 0.75 | 1.60 | 0.030 | 0.063 | |
| |
| | | | | | | | | | | | | | | |
After the Ll data cache miss, the processor performs a 32-byte burst read cycle on the system bus to fetch the data-cache line addressed by the pending write cycle. The data associated with the pending write cycle is merged with the recently-allocated cache line and stored in the processor's Ll data cache. The final MESI (Modified, Exclusive, Shared, Invalid) state of the cache line depends on the state of the WB/WT# and PWT signals during the burst read cycle and the subsequent cache write hit.
