| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| MP1289 | TI | DIP | in stock | 160 |
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| MP1289 | 1005 |
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| MP1289 | TI | DIP | 50 |
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| MP1289 | TI | DIP | STRC Verified | 255 |
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| MP1289 | TI | DIP | STRC Verified | 255 |
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| MP1289 | TI | 00+05+ | DIP/SOP/QFP | 5 |
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| MP1289 | TI | . | callmeanytime | 125 |
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MP1289 Datasheet
MP1289 on stock C-E Saturation Voltage B-E Saturation Voltage Gain-Bandwidth Product Output Capacitance C-B Breakdown Voltage C-E Breakdown'Voltage E-B Breakdown Volta8e C-E Sustain Voltage C-E Sustain Voltage SCL (Pin 10): This is the SMBus clock input pin. Data is shifted into the SDA pin at the rising edges ofthe SCL clock during data transfer. SCL is a high impedance pin. SCL requires a pull-up resistor or current source to Vcc. OR/XOR/CASCADE Logic The ATF1516AS's logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5- input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay. The macrocell's XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinato- rial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops. |
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