MW201 Datasheet| INPUT CHARACTERISTICS | Limits | Units | | Minimum Control Current ( See flaurel) | 2.0 | mA | | Maximum Control Current for Off-State Resistance @TA=+250C | 0.4 | mA | | Control Current Range (Caution: current limit input LED, see figure 5) | 2.0 t0 25 | mA | | Maximum Reverse Voltage | 7.0 | V | | | |
MW201 Price| | Symbol | | Typ | | | | | Collector-base breakdown voltage | | | | | V | lc:iOOyA | | Collector-emitter breakdown voltage | | | | | v | | | Emitter-base breakdown voltage | | | | | v | E:100UA | | | | | | | UA | | | | | | | | yA | | | Collector-emitter saturation voltage | VCE(sa~) | | | | v | | | | | | | | Base-emitter saturation voltage | VBE(satl | | | | V | | | | | 1 2 | | | | | | | | | VCE:1V, lc=O.imA | | | | | VCE:1V, lc=imA | | | | | VCE:1V, lc=iOmA | | | | | VCE:1V, lc=150mA | | | | | VCE:2V, lc=500mA | | | fT | | | | | VCE=10V, IE:-20mA, f=iOOMHz | | Collector output capacitance | Cob | | | | pF | VCB=10V, f:iOOkHz | | Emitter input capacitance | Cib | | | | pF | VEB=0.5V, f=iOOkHz | | Delay time | | | | | | Vcc:30V, VEBIOFFI:2V, lc=150mA, IBl=15mA | | | tr | | | | | Vcc=30V, VEBIOFFI:2V, lc=150mA, IBl=15mA | | Storage time | tstg | | | | | Vcc=30V, lc=150mA, IBl=-IB2=15mA | | | tf | | | | | Vcc:30V, lc=150mA, IBl=-IB2=15mA | | | | | | | |
MW201 on stock| Pin No | Pin Name | Function | Notes | | 1 | Vssl | Ground | Ground connection (digital system ground) | | 2 | XtaIIN | | These pins are used either to connect the crystal and capacitors used to form an external | | 3 | XtaIOUT (MUTE) | Crystal oscillator (MUTE input) | crystal oscillator circuit to generate the internal synchronizing signals, or to input an external clock signal (2fse or 4fsc). As a mask option, the XtaIOUT pin can be set to function as the MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pull- up resistor is built in and the input has hysteresis characteristics.) | | 4 | CTRL1 (CHABLK) | Crystal oscillator input switching (CHABLK output) | Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRLl input pin can be set to function as the CHABLK (character . frame) output. This is a 3-value output. | | 5 | HFTONOUT | Background line output | Outputs the_range signal specified by LNA*, LNB*, and LNC*. Outputs the crystal oscillator clock when RST is low. (This signal is not output after a reset command is executed.) | | 6 | OSCIN | | Connections for the inductor and capacitor that form the character output dot clock generation | | 7 | OSCOUT | LC oscillator | oscillator. | | 8 | SYNCJDG | External synchronizing signal judgment output | Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a high level when synchronizing signals are present. Outputs the dot clock (LC oscillator) when RST is low. (This signal is not output on command resets.) | | 9 | cs | Enable input | Serial data input circuit enable pin. Serial data input is enabled when a low level is input. A pull-up resistor is built in. (This input has hysteresis characteristics.) | | 10 | SCLK | Clock input | Serial data input circuit clock input. A pull-up resistor is built in. (This input has hysteresis characteristics.) | | 11 | SIN | Data input | Serial data input. A pull-up resistor is built in. (This input has hysteresis characteristics.) | | 12 | VDD2 | Power supply | Composite video signal level adjustment power supply (analog system power supply) | | | | |
INo products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss.
|
