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MX045-32M0000 Price

MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). EMRS cycle with address key programs. All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation. Special Function Support. -. PASR (Partial Array Self Refresh). -. TCSR (Temperature Compensated Self Refresh). DQM for masking. Auto refresh. 64ms refresh period (8K cycle). Commercial Temperature Operation (-25'C ~ 700C). 54balls CSP (-RXXX - Pb, -BXXX - Pb Free).
MX045-32M0000 on stock

SYMBOL	PARAMETER	CONDITIONS	TYP.	MAX	UNIT
VF	forward voltage	IF= 50 mA	0.9	1.1	V
IR	reverse leakage current	VR= 30V		20	nA
Cd	diode capacitance	VR = 0 V; f= 1 MHz	570		fF
		VR = 1 V; f= 1 MHz	400		fF
		VR = 5 V; f= 1 MHz	270		fF
		VR = 20 V; f= 1 MHz	200	250	fF
rD	diode forward resistance	IF = 0.5 mA; f = 100 MHz	77	100	l
		IF = 1 mA; f= 100 MHz	40	50
		IF = 10 mA; f= 100 MHz	5.4	7	l
		IF = 100 mA; f= 100 MHz	1.4	1.9	l
TL	charge carrier life time	when switched from IF = 10 mA to IR =6 mA; RL = ioo I ; measured at IR = 3 mA	1.25		o[S
Ls	series inductance	IF = 100 mA; f= 100 MHz	1.5		nH

Each receiver is quadruply buffered to minimize the potential of receiver over-run or to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided to disable a remote DUART transmitter when the buffer of the receiving device is full.

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