| 1tems | Symbols | Ratings | Units |
| ]9· | VCBO | 1400 | V |
| ]·y | VCEO | 1400 | V |
| ]·-yla | VCEO(SUS) | | V |
| {~yK | VEBO | 10 | V |
| | DC | lc | 50 | A |
| ]L | Ims | ICP | 100 | A |
| DC | -lc | 50 | A |
| | DC | lB | 3 | 'A |
| -Z | Ims | IBP | 6 | A |
| ] | Tran;istor | Pc | 400 | W |
| Trangicters | Pc | 800 | W |
| | TJ | +150 | 'C |
| 1 | Tstg | -40+125 | C |
| | m | 265 | g |
| | AC. Imin | Viso | 2500 | V |
| | Mounting1 | 3 5 | Kl-m |
| h J | Terminals 1 | 3 5 | N-m |
| | | | |
Implements two Utopia L3 Masters providing a solution to bridge Utopia Slave devices Compliant with ATM-Forum af-phy-0136.000 (Utopia L3) Meets 104MHz performance offering more than 622 Mbps cell rate transfers Single chip solution for improved system integration Support cell level transfer mode Cell and clock rate decoupling with on chip FIFOs Up t0 1.5 KByte of on chip FIFO per data direction Integrated management interface and built-in errored cell discard ATM Cell size programmable via external pins from 16 t0 128 bytes Optional Utopia parity generation/checking enable/disable via external pin Built in JTAG port (IEEE1149 compliant) Simulation model available for system level verification (Contact Quicklogic for details) Solution also available as flexible Soft-IP core, delivered with a full device modelization and verification testbenches
