Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the STOP condition for a write command has been issued from the master, the device initiates the internally timed write cycle. Acknowledge (ACK) polling can be initiated immediately. This involves the master sending a START condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Fig.9 for flow diagram.
| | I | I ts = +2.5V 4L = 25n | | |
| | | VS = +2.5 RL = 10{l I | V 1 | IS = +2.5V lL = 5fl / |
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| ] | j |
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