MX23L3223MC-11 Datasheet| COPPER AREA | | THERMAL RESISTANCE | | TOPSIDE" | BACKSIDE | BOARD AREA | (JUNCTION-TO-AMBIENT) | | 2500 sq mm | 2500 sq mm | 2500 sq mm | 60rC/W | | 1000 sq mm | 2500 sq mm | 2500 sq mm | 60rC/W | | 225 sq mm | 2500 sq mm | 2500 sq mm | 68rC/W | | 100 sq mm | 2500 sq mm | 2500 sq mm | 74rC/W | | | | |
MX23L3223MC-11 Price| Features 30A, 100V, RDS(on) = 0.0951 Second Generation Rad Hard MOSFET Results From New Design Concepts Gamma . Meets Pre-Rad Specifications t0 100KRAD(Si) . Defined End Point Specs at 300KRAD(S1) and 1000KRAD(Si) . Performance Permits Limited Use t0 3000KRAD(Si) Gamma Dot - Survives 3E9RAD(Si)/sec at 80% BVDSS Typically . Survives 2E12 Typically If Current Limited to IDM Photo Current . 10.OnA Per-RAD(Si)/sec Typically Neutron . Pre-RAD Specifications for 3E13 Neutrons/cm2 - Usable t0 3E14 Neutrons/cm2 Description The Intersil Corporation Sector has designed a series of SECOND GENERATION hardened power MOSFETs of both N and P channel enhancement types with rat- ings from 100V t0 500V, 1A t0 60A, and on resistance as low as 25m I . Total dose hardness is offered at 100K RAD(Si) and 1000KRAD(Si) with neutron hardness ranging from lE13 for 500V product t0 1E14 for 100V product. Dose rate hardness (GAMMA DOT) exists for rates t0 1E9 without current limiting and 2E12 with cur- rent limiting. This MOSFET is an enhancement-mode silicon-gate power field effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to exhibit minimal characteristic changes to total dose (GAMMA) and neutron (no) exposures. Design and processing efforts are also directed to enhance survival to heavy ion (SEE) and/or dose rate (GAMMA DOT) exposure. This part may be supplied as a die or in various packages other than shown above. Reliability screening is available as either non TX (commercial), TX equivalent of MIL-S-19500, TXV equivalent of MIL-S-19500, or space equivalent of MIL-S-19500. Contact the Intersil Corporation High-Reliability Marketing group for any desired deviations from the data sheet. | Package T0-258AA Symbol D G S | | Absolute Maximum Ratings (TC = +250C) Unless Otherwise Specified FRE9160D, R, H UNITS Drain-Source Voltage. . . . . . . . . . . . . . . . . .VDS -100 V Drain-Gate Voltage (RGS = 20kI ) ' ' ' ' ' ' . . . . . . . VDGR -100 V Continuous Drain Current Pulsed Drain Current . . . . . . . . . . . . . . . . . . IDM 90 A Gate-Source Voltage . . . . . . . . . . . . . . . . . .VGS +20 V Maximum Power Dissipation Derated Above +250C . . . . . . 1.20 W/oC Inductive Current, Clamped, L = 100ffH, (See Test Figure~ . . . . . . . . . ILM 90 A Continuous Source Current (Body Diode~ . . . . . . . . . . .IS 30 A Pulsed Source Current (Body Diode) . ' ' ' . . . . . . . . . ISM 90 A Operating And Storage Temperature. . . . . . . . TJC, TSTG -55 to +150 0C Lead Temperature (During Soldering) Distance > 0.063 in. (1.6mm) From Case, 10s Max. . . . . . . . . . . . . . . . . . TL 300 0C | | |
MX23L3223MC-11 on stock| Parameter | Symbol | Min | Max | Unit | | CLE Set-up Time | tCLS | O | | ns | | CLE Hold Time | tCLH | 10 | | ns | | CE Setup Time | tcs | 0 | | ns | | CE Hold Time | tCH | 10 | | ns | | WE Pulse Width | tWP | 25 | | ns | | ALE Setup Time | tALS | O | | ns | | ALE Hold Time | tALH | 10 | | ns | | Data Setup Time | tDS | 20 | | ns | | Data Hold Time | tDH | 10 | | ns | | Write Cycle Time | twc | 50 | | ns | | WE High Hold Time | tWH | 15 | | ns | | | | | |
| Parameter | Value | Units | | DC Power Supply | 5.0 | V | | Power Dissipation | 500 | mW | | Operating Temperature | -40 t0 85 | C | | Storage Temperature | -60 t0 150 | C | | Signal level on inputs/outputs | +20 | dBm | | Voltage to any non supply pin | +0.3 | V | | | |
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