MX27C1000ATI-15 Datasheet The KA78R05 is a low-dropout voltage regulator suitable for various electronic equipments. It provides constant voltage power source with T0-220 4 lead full mold package. Dropout voltage of KA78R05 is below 0.5V in full rated current(lA). This regulator has various function such as peak current protection, thermal shut down, overvoltage protection and output disable function. MX27C1000ATI-15 Price| PARAMETER | SYM | TEST CONDITIONS | MIN | TYP | MAX | UNIT | | Input Low Voltage | VIL | | -0.5 | | +0.8 | V | | Input High Voltage | VIH | | +2.0 | | VDD +0.3 | V | | Input Leakage Current | ILI | VIN = Vsso to VDDQ | -10 | | +10 | A | | Output Leakage Current | ILO | Viio = Vsso to VDDQ, and data I/O pins in high-Z state defined in truth table | -10 | | +10 | A | | Output Low Voltage | VOL | IOL=+8.0 mA | | | 0.4 | V | | Output High Voltage | VOH | IOH=-4.0 mA | 2.4 | | | V | | Operating Current | IDD | TCYC > min. , l/0 = 0 mA | | | 350 | mA | | Standby Current | ISB | Unselected mode defined in truth table, VIN, Vio = VIH (min.) NIL (max.) TCYC > min. | | | 80 | mA | | ZZ Mode Current | lzz | ZZ mode, TCYC > min. | | | 5 | mA | | | | | | | |
MX27C1000ATI-15 on stock Package Power Ratings at 700C TSK 4604 ...... 0.50 ... 0.60 ... 0.8 watts 4605 ...... 0.63 ... 0.75 ... 1.0 watts 4606 ...... 0.75 ... 0.90 ... 1.2 watts 4607 ...... 0.88 ... 1.05 ... 1.4 watts 4608 ...... 1.00 ... 1.20 ... 1.6 watts 4609 ...... 1.13 ... 1.35 ... 1.8 watts 4610...... 1.25 ... 1.50 ... 2.0 watts 4611 ...... 1.38 ... 1.65 ... 2.2 watts 4612 ...... 1.50 ... 1.80 ... 2.4 watts 4613 ...... 1.63 ... 1.95 ... 2.6 watts 4614 ...... 1.75 ... 2.10 ... 2.8 watts | Parameter | Description | Conditions | Min | Typ. | Max | Unit | | ICLKFR | Input Clock Frequency Range | Non-crystal, 3.OV Pk-Pk ext. source | 25 | | 200 | MHz | | tRISE(a) | Clock Rise Time | SSCLKla or SSCLKlb, Freq = 100 MHz | 1.0 | 1.3 | 1.6 | ns | | tFALL(a) | Clock Fall Time | SSCLKla or SSCLKlb, Freq = 100 MHz | 1.0 | 1.3 | 1.6 | ns | | 'RlSE(a+b) | Clock Rise Time | SSCLKl(a+b), CL = 33 pF, 100 MHz | 1.2 | 1.5 | 1.8 | ns | | tFALL(a+b) | Clock Fall Time | SSCLKl(a+b), CL = 33 pF, 100 MHz | 1.2 | 1.5 | 1.8 | ns | | oRlSE(a+b) | Clock Rise Time | SSCLKl(a+b), CL = 33 pF, 200 MHz | 1.1 | 1.4 | 1.7 | ns | | tFALL(a+b) | Clock Fall Time | SSCLKl(a+b), CL = 33 pF, 200 MHz | 1.1 | 1.4 | 1.7 | ns | | oRlSE(REF) | Clock Rise Time | REFOUT, Pin 3, CL = 15 pF, 50 MHz | 1.0 | 1.3 | 1.6 | ns | | oFALL(REF) | Clock Fall Time | REFOUT, Pin 3, CL = 15 pF, 50 MHz | 1.0 | 1.3 | 1.6 | ns | | DTYin | Input Clock Duty Cycle | XIN/CLK (Pin) | 30 | 50 | 70 | % | | DTYout | Output Clock Duty Cycle | SSCLKla/b (Pin 8 and 9) | 45 | 50 | 55 | % | | CCJ1 | Cycle-to-Cycle Jitter | F = 100 MHz, SSCLKla/b CL = 33 pF | | 300 | 400 | ps | | CCJ2 | Cycle-to-Cycle Jitter | F = 200 MHz, SSCLKla/b CL = 33 pF | | 500 | 600 | ps | | REFOUT | Refout Frequency Range | CL= 15 pF | 25 | | 108 | MHz | | | | | | | |
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