MX28F160C3BTC-70 Datasheet| | | | | M27C64A | | | Symbol | Alt | Parameter | Test Condition | ·15 | -20 | -25 | -30 | Unit | | Min | Max | Min | Max | Min | Max | Min | Max | | LAV@ | tACC | Address Valid to Output Valid | E = VIL, G = VIL | | 150 | | 200 | | 250 | | 300 | ns | | tELQV | tCE | Chip Enable Low to Output Valid | G= VIL | | 150 | | 200 | | 250 | | 300 | ns | | tGLQV | tOE | Output Enable Low to Output Valid | E= VIL | | 75 | | 80 | | 100 | | 120 | ns | | tEHQZ(2) | tDF | Chip Enable High to Output Hi-Z | G= VIL | O | 50 | O | 50 | 0 | 60 | O | 105 | ns | | tGHQZ(2) | tDF | Output Enable High to Output Hi-Z | E= VIL | O | 50 | O | 50 | 0 | 60 | O | 105 | ns | | LAXOX | tOH | Address Transition to Output Transition | E = VIL, G = VIL | O | | O | | 0 | | O | | ns | | | | | | | | | | | | | | MX28F160C3BTC-70 Price| i | | | | | | | | | | | | ____ | | | | | I | | | | | | | | | | | | | | | | | | | | | | | | | | Te - | § | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | F --+ c.) Im l.ib:A)Ims | | | | | | | | | | | | MX28F160C3BTC-70 on stock| | | FIGURE No. | TN41A | TN41B | | | CHARACTERISTIC | SYMBOL | AND CONDITION | MIN | TYP | MAX. | MIN | TYP | MAX. | UNIT | | Peak Current | RG =1Mfl | | | | 0.05 | 2 | | 0.01 | 0.15 | | | (VS =10V) | RG =10kfl | Ip | 1,2,3 | | 1.0 | 5 | | 0.35 | 1.0 | A | | Offset Voltage | RG =1Mfl | | | 0.2 | 0.35 | 1.6 | 0.2 | 0.35 | 0.6 | V | | (VS =10V) | RG =10kfl | VT | 1,2,3 | 0.2 | 0.45 | 0.6 | 0.2 | 0.45 | 0.6 | | Valley Current | RG =1Mfl | | | | 15 | 50 | | 7 | 25 | | | (VS =10V) | RG =10kfl | IV | 1,2,3 | 70 | 200 | | 25 | 160 | | A | | Gate-Anode Leakage Current | IGAO | 4VS =40V | | O03 | 10 | | 0.03 | 10 | nA | | Gate-Cathode Leakage Current | IGKS | 5VS =40V | | 0.3 | 100 | | 0.3 | 100 | nA | | Forward Voltage | VF | IF= 50mA | | 1 | 1.5 | | 1 | 1.5 | V | | Pulse Output Voltage | VO | 6.7 | 6 | 10 | | 6 | 10 | | V | | Pulse Voltage Rise Time | tr | 6.7 | | 70 | 80 | | 70 | 80 | ns | | | | | | | | | | | |
(AII Pin Designations Refer t0 40-Pin DIP Package) The TC811 is a dual slope, integ rating analog-to-digital converter. An understanding of the dual slope conversion technique will aid the user in following the detailed TC811 theory of operation following this section. A conventional dual slope converter measurement cycle has two distinct phases: 1) Input Signal Integration 2) Reference Voltage Integration (Deintegration) Referring to Figure 2, the unknown input signal to be converted is integrated from zero for a fixed time period (TINT), measured by counting clock pulses. A constant reference voltage of the opposite polarity is then integrated until the integrator output voltage returns to zero. The reference integration (deintegration) time (TDEINT) is then directly proportional to the unknown input voltage (VIN). In a simple dual slope conve rter, a complete conversion requires the integrator output to "ramp-up" from zero and "ramp-down" back to zero. A simple mathematical equation relates the input signal, reference voltage and integration time: |