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Part Numbert	Mfg	Packt	D/C	Descriptiont	Qty	Company/Contact
MX29F016TI90	N/A	vivian@ave	2000+	New original	19316	shanghai cydz Technology Co., .. Contact:zhou Tel:86-21-60953587 Fax: Email: cydz666@163.com

MX29F016TI90 Datasheet

PIN NUMBER	SYMBOL	FUNCTION
1	GND	Ground
2	CE/	Chip Enable (-ve logic)
3	C1+	External Capacitor +Pin
4	VOUT	Reverse Output Pin
5	VIN	Power Supply Pin
6	C1-	External Capacitor -Pin

MX29F016TI90 Price

81-88	81-88	CA15 - CA8	O	Controller Address Bus
90-93,95-98	90-93,95-98	CA7 - CAO	O	Controller Address Bus
99-106	99-106	D7- DO	I/O	Controller Data Bus
1 08	1 08	FR SP2	I/O	Frame Signal Of Serial Port 2
1 09	1 09	FR SP1	I/O	Frame Signal Of Serial Port 1
1 1 0	1 1 0	/POR	O	DSP Reset Output
1 1 1 1 12	1 1 1 1 12	VOICE Sel 1 VOICE Sel 2	O	Modem Control Output Memory map is bit l-2 0f DAA at memory address DOOOH
1 14	1 14	CODEC CLK	O	20.16MHz Clock Output For DM6580 Chip
1 1 5	1 1 5	OSCO	O	Optional Codec X'tal clock output
1 16	1 16	OSCI	O	Optional Codec X'tal clock input
1 1 9	1 1 9	TD SP2	O	Data Output Pin Of Serial Port 2 The serial data is clocked out through this pin according to the rising edge of SCLK. The MSB is sent immediately after the falling edge of the FR_SP2 signal.
120	120	PS1	O	Modem Control Port Select Output: Memory address mapping of the controller is D800H.
122	122	EXT/INTB	l	Select Pin: Used to select internal or external operation. 0: internal modem 1: external modem
	7,14~17,26, 27,38~41,44, 53~56,64,65, 75,121, 124~127	NC	N	External only

MX29F016TI90 on stock

Multilayer construction also permits the routing of sen- sitive signal traces away from high-level, high-speed signal lines. To minimize the possibility of coupling noise into the receiver section, high-level, high-speed signals such as transmitter inputs and clock lines should be routed as far away as possible from the receiver pins.

0	Number of bytes utilized by module manufacturer	1	0	0	0	0	0	0	0	80H	128 bytes
1	Total number of bytes in serial PD device	0	0	0	0	1	0	0	0	08H	256 bytes
2	Memory type	0	0	0	O	1	0	0	0	08H	DDR2 SDRAM
3	Number of row address	0	0	0	O	1	1	1	0	OEH	14
4	Number of column address	0	0	0	O	1	O	1	1	OBH	11
5	Number of DIMM ranks	0	1	1	O	O	O	O	0	60H	1
6	Module data width	0	1	0	0	1	0	0	0	48H	72
7	Module data width continuation	0	0	0	0	0	0	0	0	OOH	O
8	Voltage interface level of this assembly	0	0	0	O	O	1	O	1	05H	SSTL l.8V
9	DDR SDRAM cycle time, CL = 5 -5C	0	0	1	1	1	1	0	1	3DH	3.75ns1
9	-4A	0	1	0	1	O	O	O	0	50H	5.Ons*'
10	SDRAM access from clock (tAC) -5C	0	1	0	1	0	0	0	0	50H	0.5ns*'
10	-4A	0	1	1	O	O	O	O	0	60H	0.6ns*'
11	DIMM configuration type	0	0	0	0	0	0	1	0	02H	ECC
12	Refresh rate/type	1	0	0	O	O	0	1	0	82H	7.8s
13	Primary SDRAM width	0	0	0	O	O	1	O	0	04H	×4
14	Error checking SDRAM width	0	0	0	O	O	1	O	0	04H	×4
15	Reserved	0	0	0	O	O	O	O	0	OOH	O
16	SDRAM device attributes: Burst length supported	0	0	0	0	1	1	0	0	OCH	4,8
17	SDRAM device attributes: Number of banks on SDRAM device	0	0	0	O	0	1	0	0	04H	4
18	SDRAM device attributes: /CAS latency	0	0	1	1	1	0	0	0	38H	3.4.5
19	Reserved	0	0	0	O	O	O	O	0	OOH	O
20	DIMM type information	0	0	0	0	0	0	0	1	OIH	Registered
21	SDRAM module attributes	0	0	0	0	0	0	0	0	OOH	Normal
22	SDRAM device attributes: General	0	0	1	1	0	0	0	0	30H	VDD±O.1V
23	Minimum clock cycle time at CL = 4 -5C	0	0	1	1	1	1	0	1	3DH	3.75ns*1
23	-4A	0	1	0	1	O	O	O	0	50H	5.Ons*'
	Maximum data access time (tAC) from
24	clock at CL = 4 -5C	0	1	0	1	0	0	0	0	50H	0.5ns*'
24	-4A	0	1	1	O	O	O	O	0	60H	0.6ns*'
25	Minimum clock cycle time at CL = 3 -5C, -4A	0	1	0	1	0	0	0	0	50H	5.Ons*'
	Maximum data access time (tAC) from
26	clock at CL = 3 -5C, -4A	0	1	1	0	0	0	0	0	60H	O6ns*1

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