| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
MX574ATQ-883 MX574ATQ-883 MX574ATQ883 Datasheet
MX574ATQ-883 MX574ATQ-883 MX574ATQ883 Price A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte/s bandwidth to a system's high-speed external memory sub-system. In addition, the 80960CA's on-chip caching of instruc- tions, procedure context and critical program data substantially decouple system performance from the wait states associated with accesses to the system's slower, cost sensitive, main memory subsystem. Program, Program Inhibit, Program Verify These modes are entered by placing a high voltage VPP on pin 19, with pins 18 and 20 set to VILP In this state, pin 21 becomes a latch signal, allowing the upper 5 address bits to be latched into an onboard register, pin 22 becomes an active LOW program (PGM) signal and pin 23 becomes an active LOW verify (VFY) signal. Pins 22 and 23 should never be active LOW at the same time. The PROGRAM mode exists when PGM is LOW, and VFYis HIGH. The verify mode exists when the reverse is tnje, PGM HIGH and VFY LOW and the program inhibit mode is entered with both P~M and VFY HIGH. Program inhibitis specifically provided to allow data to be placed on and removed from the data pins without conflict |
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