MX580JCSN MX580JCSN MX580JCSN Datasheet| TC = 25UC Tj = MAX RATED I | | | | | | III I III I III I III I | | | | | | | | | J | | j | | | | | III l l | | | | | | | | j | r | | | | j | | 1 | , RFM4N35, 40 I DCPdKllfi^ | | | | | | j | DP AR LIh | ER EA I¨ITE | I M DI | C ^ 3 | iN IN TF 'BE Y rDS(C | ¨S lN1 | L | ) | | ~ | r'M | | | | | | | | | | | | | l | | | | | | | | | | | | | | | | | | RFM4N35, RFP4N35 _ | | | | | | | | | | | | | H IIIII | | l | | | | | | | | | | | | | | | | | | | | |
MX580JCSN MX580JCSN MX580JCSN Price| I | .550 t.S50; | / SEALED UNITS ONL11 | | 1 I | I . , OUT + 'P2 ' P3 + + . S2 (i + . S4 +I .u | I os) l " | RH + fiL . + + + + DC fIEF * -15V * | | 0.20 + .Ol NON CUMUt ATIVF [Jfl | | f JL | S1 (SIN) I GND. + . S3 +15V * | r- | | t | | m 1 | | | 212+ ±.05 | U i 625O' = | | | | | | | |
MX580JCSN MX580JCSN MX580JCSN on stock| | | | 70T651/9S | | | Symbol | Parameter | Test Conditions | Min | Max | Llnit | | | Input Leakage Current(l) | VDDQ = Max., VIN = OV to VDDQ | | 10 | pA | | | JTAG & ZZ Input Leakage Current(1,2) | VDD : Max., VIN = OV to VDD | | +30 | UA | | IILOI | Output Leakage Current(1'3) | CEo = VIH or CEi = VIL, VOUT = OV to VDDQ | | 10 | UA | | VOL (3.3V) | Output Low Voltage(') | IOL = +4mA, VDDO = Min. | | 0 4 | V | | VOH (3.3V) | Output High Voltage(') | IOH = 4mA, VDDO = Min. | 24 | | V | | VOL (2.5V) | Output Low Voltage(') | IOL = +2mA, VDDO = Min. | | 0 4 | V | | VOH (2.5V) | Output High Voltage(') | IOH = -2mA, VDDO = Min. | 2 0 | | V | | | | | | |
Features I Operates at 2-bit Non-Return to Zero (NRZ) Data Rates up t0 50 Mbits/second I Single +5V Power Supply Operation I Low Power Dissipation when TTL compatible code out- put is selected. 150 mW at 50 Mbits/second NRZ Rate I TTL Compatible Inputs and Outputs I ECL Compatible Code Outputs (patented) are control register selectable I Two-bit NRZ Interface I Supports Write Data Precompensation with Early and Late output signals I Selectable use of either an Internal or External Write Clock I Power Down Mode Included I DC-Erasure is available to support Analog Flaw Map- ping Testing I Bypass Mode available which permits Un-Encoded Test Patterns to be issued at the CODEOUT Pin
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