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MX758CWE-W MAXIM    08+09+  stock  1100 

MX758CWE-W Datasheet
DESCRIPTION The M74HC138 is an high speed CMOS 3 T0 8 LINE DECODER fabricated with silicon gate C2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input Gl is held low or either G2A or G2B is held high, the decoding function is
MX758CWE-W Price

-100MT...P
j
-- -I l I - -Ti=150C
f --Tj=25'C
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MX758CWE-W on stock

2SH6it(i 2SB646A
I Iem Symbol Test Condition nlI1 Lyp. 1nax n¨in ly Uni
Colleccor ro base breakdown vohage v(BR)CJlO Ic = -] OUA, J[: : o -120 -120 V
Collecior to emitttr breakdown voIcagc VCBR)CEO Ic = -lmA, ROE =* -ao -IOO v
Emitcer to base brcakdown voliage V rnR'Fn0 lr - -IOpAt lc = O 5 5 V
Collector cuIOfrc:urrenl ICBO V{:B = -IOOV;IE = O -10 -10 ^
DC currcnt cransfcr racio hI Vcr= -5v1c=-lOmA 60 320 60 2(X)
|1FE2 VCE -5Vt lc - -ImA 30 30
Collecior to emiUer saiuration voltagc VCFn lc = -30mA,In =3rnA -2 2 V
Base io emiirer voltage VRE VcF: = -5 V. lc = - ] OmA I5 -l5 V
Gain bandwidch produc{ VCF. = -5Vt lC= -lOmA. 140 140 MHz
Collector output capacicance C Vc = --lOV. IE = O, f = IMHz 4 4 pF


Parameter remp Test Level Min Typ Max Unit
WRITE OPERATION (See Figure 46) SCLK Clock Rate (fSCLK) SCLK Clock High (tHI) SCLK Clock Low (tLOW) SDIO to SCLK Setup Time (tDS) SCLK to SDIO Hold Time (tDH) SEN to SCLK Setup Time (ts) SCLK to SEN Hold Time (tH) Full Full Full Full Full Full Full IV IV IV IV IV IV IV 32 14 14 14 0 14 0 MHz ns ns ns ns ns ns
READ OPERATION (See Figure 47 and Figure 48) SCLK Clock Rate (fSCLK) SCLK Clock High (tHI) SCLK Clock Low (tLOW) SDIO to SCLK Setup Time (tDS) SCLK to SDIO Hold Time (tDH) SCLK to SDIO (or SDO) Data Valid Time (tDV) SEN to SDIO Output Valid to Hi-Z (tEZ) Full Full Full Full Full Full Full IV IV IV IV IV IV IV 32 14 14 14 0 14 2 MHz ns ns ns ns ns ns