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MX8810 Datasheet

Test Conditions Value
Symbol Parameter Vcc TA = 25 0C 54HC and 74HC -40 t0 85 0C 74HC -55 t0 125 0C 54HC Unit
(V) Min Typ. Max Min Max Min Max
tTLH tTHL Output Transition Time 4.5 8 15 19 23 ns
tPLH tPHL Propagation Delay Time 4.5 15 24 30 36 ns
CIN Input Capacitance 5 10 10 10 pF
CPD(+) Power Dissipation Capacitance 48 pF


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Features 1.25 Micron Radiation Hardened SOS CMOS Total Dose 300K RAD (Si) Single Event Upset (SEU) Immunity Pinouts 14 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C TOP VIEW
<1 x 10'10 Errors/Bit-Day (Typ) SEU LET Threshold >80 MEV-cm2/mg Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse Latch-Up Free Under Any Conditions Military Temperature Range: -55aC to +1250C Significant Power Reduction Compared to ALSTTL Logic A1 B1 Y1 A2 B2 Y2 GND vcc B4 A4 Y4 B3 A3 Y3
DC Operating Voltage Range: 4.5V t0 5.5V Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2V Min Input Current "1ccA at VOL, VOH 14 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP3-F14, LEAD FINISH C TOP VIEW A1 1 1 14 . VCC
Description The IntersiIACTSOOMS is a radiation hardened quad 2-Input NAND gate. A high logic level on both inputs forces the output to a logic low state. The ACTSOOMS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radia- HI B1 Y1 A2 i B2 i Y2 i GND 2 13 3 12 4 11 5 10 6 a 7 8 B4 A4 Y4 B3 A3 Y3
tion hardened, high-speed, CMOS/SOS Logic Family.
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE
ACTSOODMSR -550c to +1250C Intersil Class S Equivalent 14 Lead SBDIP
ACTSOOKMSR -550c to +1250C Intersil Class S Equivalent 14 Lead Ceramic Flatpack
ACTSOOD/Sample +250C Sample 14 Lead SBDIP
ACTSOOK/Sample +250C Sample 14 Lead Ceramic Flatpack
ACTSOOHMSR +250C Die Die
Truth Table Functional Diagram
INPUTS OUTPUT
An Bn Yn >
L L L H H H [1> Yn _
H L H k '7 y
H H L
NOTE: L = Logic Level Low, H = Logic Level High


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SPECIFICATIONS
Test Conditions Limits B Suffix -25 t0 85IC
Parameter Symbol Unless Otherwise Specifieda LL = VDD, 2.7 V " VDD, VS " 6.0 V, GND = PGND Minb Typ Maxb Unit
Output Drive (DR and Ds)
Output High Voltage VOH VDD = 2.7 V IOUT= -10 mA 5 15 5 2 V
Output Low Voltage VOL Vs = 5.3 V IOUT= 10 mA 0 06 0 15
Peak Source Output Current oSOURCE VDD= 2.7V Vs= 5.3V -300 -250 mA
Peak Sink Output Current ISINK VS= 5.3V 250 300
Break-Before-Make oBBM VDD= 6.0V 40 ns
Logic
ENABLE Delay to Output tdEN ENABLE Rising to OUTPUT, VDD = 6.0 V 1 4 l_ls
ENABLE Logic Low VENL 0.2 VDD V
ENABLE Logic High VENH 0.8 VDD
ENABLE Input Current IEN ENABLE = 0 to VDD -1.0 1 0 pA
Light Load Delay to Outpute tdLL Light Load Falling to OUTPUTS 1 4 l_ls
Light Load Logic Low VLLL O8 V
Light Load Logic High VLLH 2.4
Light Load Input Current ILL LL=0to VDD -1.0 1 0 pA
Duty Cycle
Maximum Duty Cycle CYCLEMAX VDD= 6.0V 80 95 %
DMAX/SS Input Current oDMAX DMAX = 0 to VDD -100 100 nA
Supply
Supply Current-Normal No Load. VLL = O to VDD , VDD= 2.7V 1 1 1 5 mA
Mode IDD fosc = 1 MHz, Rosc = 7.0 kl VDD= 4.5V 1 6 2 3
Supply Current-Standby Mode ENABLE= Low 250 330 UA