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MXD1000SA200 Datasheet

ID r	iax (pulse)*

		10 rT	1S}1

*: Single pulse Ta = 250C Curves must be derated linearly with increase in					1ax
temperature				VDSS II

MXD1000SA200 Price

Sze - 1- up half-size: 2.58" x 2.5" x 0.62" (65,5 x 63,5 x 15,7mm) Sze - 1- up full-size: 4.9" x 2.5" x 0.62" (124,5 x 63,5 x 15,7m m) Sze - 2- up half-size: 2.58" x 4.9" x 0.62" (65,5 x 124,5 x 15,7m m) Sze - 2- up full-size: 4.9" x 4.9" x 0.62" (124,5 x 124,5 x 15,7m m) Sze - 3- up half-size: 2.58" x 7.3" x 0.62" (65,5 x 185,4 x 15,7m m) Sze - 3- up full-size: 4.9" x 7.3" x 0.62" (124,5 x 185,4 x 15,7m m)
MXD1000SA200 on stock

(+) In= Nominal current according to ISO definition for high side automotive switch (see note l) (^) See switching time waveform () The VH iS internally clamped at 6V about ltis possible to connect this pin to an higher voltage via an external resistor calculated to not exceed 10 mA at the input pin. note l: The Nominal Current is the current at Te = 85 0C for battery voltage of 13V which produces a voltage drop of 0.5 V note 2: IOL(off) = (Vce -VOL)/ROL note 3: tpovl tpol: ISO definition

Description [1]	Symbol	Unit	min	typ	max
General
Oscillator Input period on OSC1		ns	164		170
Rising time of SDO	t1	ns		20
Falling time of SDO	t2	ns		7
SCK period	t3	ns	600		Step
High time SCK [2]	t4	ns	345
Low time SCK [2, 3]	t5	ns	255
Data IN
Setup time of SCK after rising edge of SIN	t6	ns	170
Hold time of SIN after last rising edge of SCK	t7	ns	170
Setup time of INT-Signal after rising edge of SIN	t8	ns			200
Hold time of INT-Signal after falling edge of SIN	t9	ns	165
Setup time of Data on SDI before rising edge of SCK	tlo	ns	170
Hold time of Data on SDI after falling edge of SCK	t11	ns	O
Data OUT
Setup time of SDI-pulse after falling edge of SIN	t12	ns	170
Setup time of SIN after last falling edge of SCK	t13	ns	170
High time of SDI-pulse	t14	ns	255
Setup time of Data on SDO after falling edge of SDI-pulse	t15	ns			280
Setup time of SCK after falling edge of SDI-pulse	t16	ns	170
Setup time of Data on SDO after falling edge of SCK	t	ns			365
Notes: [1] Capacitive load of 50 pF [2] Can be asymmetrical [3] The low time of SCK between the last bit of a byte and the first bit of the next byte must be at least 510 ns.

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