| Name | Type | Description |
| A312 | O S H(Z) R(Z) | ADDRESS BUS carries the physical address' upper 30 bits. A31 is the most significant address bit; A2 is the least significant. During a bus access, A31:2 identify all external addresses to word (4-byte) boundaries. The byte enable signals indicate the selected byte in each word. During burst accesses, A3:2 increment to indicate successive data cycles. |
| D310 | uo S(L) H(Z) R(Z) | DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configu- ration. The least significant bit of the data is carried on DO and the most significant on D31. When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-bit data bus widths, D15:0 are used. For 32-bit bus widths the full data bus is used. |
| BE30 | 0 S H(Z) R(1) | BYTE ENABLES select which of the four bytes addressed by A31:2 are active during an access to a memory region configured for a 32-bit data-bus width. BE3 applies to D31:24; BE2 applies to D23:16; BEl applies to D15:8 BEO applies to D7:0. 32-bit bus: BE3 -Byte Enable 3 -enable D31:24 BE2 -Byte Enable 2 -enable D23:16 BEl -Byte Enable 'I -enable D15:8 BEO -Byte Enable 0 -enable D7:0 For accesses to a memory region configured for a 16-bit data-bus width, the processor uses the BE3, BEl and BEO pins as BHE, A1 and BLE respectively. 16-bit bus: BE3 -Byte High Enable (BHE) -enable D15:8 BE2 -Not used (driven high or low) BEl -Address Bit l (A1) BEO -Byte Low Enable (BLE) -enable D7:0 For accesses to a memory region configured for an 8-bit data-bus width, the processor uses the BEl and BEO pins as Al and AO respectively. 8-bit bus: BE3 -Not used (driven high or low) BE2 -Not used (driven high or low) BEl -Address Bit l (A1) BEO -Address Bit 0 (AO) |
| W/R | 0 S H(Z) R(O) | WRITE/READ is asserted for read requests and deasserted for write requests. The W/R signal changes in the same clock cycle as ADS. It remains valid for the entire access in non-pipelined regions. In pipelined regions, W/R is not guaranteed to be valid in the last cycle of a read access. |
| ADS | 0 S H(Z) R(1) | ADDRESS STROBE indicates a valid address and the start of a new bus access. ADS is asserted for the first clock of a bus access. |
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