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PAL16L8A2MJ Datasheet

TYPICAL OPERATING CONDITIONS (Class B without grid current, 2 valves) Anodevoltage . ' I . . 2.0 Screenvoltage + . . . 500 500 '... Gridvoltage . . . . . . . -88 -91 Peak a.f. input voltage (gridtogrid) . . . . . . . 172 178 Maximum-signalanodecurrent 2 x 150 2 x 155 Zero-signalanodecurrent . . . 2 x 50 2 x 50 Maximum-signal screen current 2 x 14 2 x 10 Effectiveload(anodetoanode) . . 14.5 18 Anodedissipation . . . . 2x105 2x132 Output power . ' ' . . N . 390 510 Efficiency . . . ' ' . . . . 65 66 Total distortion .
PAL16L8A2MJ Price

Items	Symbol	Ratings	Unit
Power Dissipation	PTnT	1.0	W
Power Derating (above 50 0C)		6.67	mW/oC
Forward Voltage @lf = 200 mA	Vf	1.5	V
Vz Tolerence		5	%
Junction Temp.	T J	-65 t0 175	oC
Storage Temp.	TqTr:	-65 t0 175	oC

PAL16L8A2MJ on stock

PARAMETER	SYMBOL	MIN	MAX	UNITS	TEST CONDITIONS	NOTE
On State Collector Current 4N22 4N23 4N24	lCfoNl	0.15 0.2 0.4		mA	VCE = 5V, lB = O, IF = 2mA
On State Collector Current 4N22 4N23 4N24	IC(ON)	2.5 6 10		mA	VCE = 5V, lB = 0, IF = 10mA
On State Collector Current 4N22 -550C 4N23 4N24	IC(ON)	1 2.5 4		mA	VCE = 5V, lB = O, IF = 10mA
On State Collector Current 4N22 +100'C 4N23 4N24	IC(ON)	1 2.5 4		mA	VCE = 5V, lB = O, IF = 10mA
Off State Collector Current +250C	lC(OFFl		100	nA	VCE = 20V, lB = 0, IF = OmA
Off State Collector Current +1000C	lC(OFF)		100		VCE = 20V, lB = 0, IF = OmA
Collector-Emitter Saturation Voltage 4N22 4N23 4N24	VCE(SAT) VCE(SAT) VCE(SAT1		0 3 0 3 0 3	V V V	lc = 2.5mA, lB = O, IF = 20mA lc = 5mA, lB = O, IF = 20mA lc = lOrnA, lB = O, IF = 20rriA
Input to Output Resistance ALL	Rl_0	101 l			VIN-OUT= 1kV	1
Input to Output Capacitance ALL	cl-0		5	pF	F = 1MHz, VIN-OUT= 1kV	1
Rise Time 4N22 4N23 4N24	tr tr tr		15 15 20	US US US	Vcc = 10V, IF = 10mA, RL = 100Q
Fall Time 4N22 4N23 4N24	tf tf tf		15 15 20	US US US	Vcc = 10V, IF = 10mA, RL = 100fl

When the SHIFT/LOAD input is held low,the parallel data is loaded synchronously into the register at positive going transition of the clock pulse. The CK-INH input should be shifted high only when the CK input is held high. An Input protection circuit ensures that o t0 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V t0 3V systems and on two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.

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