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PAL16P1AJM Datasheet

Parameter	Symbol	Min Typ Max	Unit
RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Startup Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid	tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF	1.0 162.8 1.3 19.5 162.8 12.288 81.4 750 32.56 42 48.84 32.56 38 48.84 48.0 20.8 5 2.5 5 2 4 10 2 4 10 2 4 10 2 4 10 2 4 10 2 4 10 2 4 10 2 4 10 0 10 15 25 15 50 15	Lrs ns ns MHz ns ps ns ns kHz ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns

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Organisation of Protection Word The Protection word protects EEPROM words from being written. The bits in protection word are one time programmable (OTP) which means that once they have been set t0 1 they can not be reset to O any more. Every EEPROM word is protected by a bit pair in Protection word. State 00 0f the pair means that the word is not protected, state 11 means write protection. 01 and 10 states are not allowed. Due to the OTP feature of bits in Protection word a word once protected becomes read only and can not be reverted back to RW. Please note that it is possible to protect the Protection word itself, in that case the protection system is locked and cannot be changed any more.
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BiMOS II devices have higher data-input rates than the original BiMOS circuits. With a 5 V supply, they will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. The CMOS inputs are compatible with standard CMOS and NMOS logic levels. TTL circuits may require the use of appropri- ate pull-up resistors to ensure a proper input-logic high. A CMOS serial data output, allows cascading these devices in multiple drive-line applications required by many dot matrix, alphanumeric, and bar graph displays.

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