| Pin | | | |
| BGA | QFN | Name | I0 | Description |
| C2 | 1 | OLS (Note 3) | Input | Input Pin for the Output Level Select (OLS). See Table 2. |
| C1 | 2 | SEL | ECL, CML, LVCMOS, LVDS, LVTTL Input | Inverted Differential Select Logic Input. |
| B1 | 3 | SEL | ECL, CML, LVCMOS, LVDS, LVTTL Input | Noninverted Differential Select Logic Input. |
| B2 | 4 | VTSEL | | Common Internal 50 Q Termination Pin for SEL/SEL. See Table 7. (Note l) |
| A1 | 5 | VTD1 | | Internal 50 Q termination pin. See Table 7. (Note l) |
| A2 | 6 | D1 | ECL, CML, LVCMOS, LVDS, LVTTL Input | Noninverted Differential Input l. Internal 75 kQ to VEE. |
| A3 | 7 | D1 | ECL, CML, LVCMOS, LVDS, LVTTL Input | Inverted Differential Input l. Internal 75 kQ to VEE and 36.5 kQ to Vcc. |
| A4 | 8 | VTD1 | | Internal 50 Q Termination Pin. See Table 7. (Note l) |
| B3 | 9 | Vcc | | Positive Supply Voltage (Note 2) |
| B4 | 10 | Q | RSECL Output | Noninverted Differential Output. Typically Terminated with 50 Q Resistor to VTT = VCC - 2 V. |
| C4 | 11 | | RSECL Output | Inverted Differential Output. Typically Terminated with 50 Q Resistor to VTT = VCC - 2 V |
| C3 | 12 | VEE | | Negative Supply Voltage (Note 2) |
| D4 | 13 | VTDO | | Internal 50 Q Termination Pin. See Table 7. (Note l) |
| D3 | 14 | DO | ECL, CML, LVCMOS, LVDS, LVTTL Input | Inverted Differential Input 0. Internal 75 kQ to VEE and 36.5 kQ to Vcc. |
| D2 | 15 | DO | ECL, CML, LVCMOS, LVDS, LVTTL Input | Noninverted Differential Input 0. Internal 75 kQ to VEE. |
| D1 | 16 | VTDO | | Internal 50 Q Termination Pin. See Table 7. (Note l) |
| N/A | | EP | | Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit. |
| | | | |
| Parameter | Symbol | CSFB 201 | CSFB 202 | CSFB 203 | CSFB 204 | CSFB 205 | Unit |
| Max. Repetitive PeakReverse Voltage | VRRM | 50 | 100 | 200 | 400 | 600 | v |
| Max. DC BlockingVoltage | VDC | 50 | 100 | 200 | 400 | 600 | v |
| Max. RMS Voltage | VRMS | 35 | 70 | 140 | 280 | 420 | V |
| Peak Surge Forward Current 8.3ms single halfsine-wave superimposed on rateload ( JEDEC method) | IFSM | 50 | A |
| Max. Average Forward Current | 1 0 | 2.0 | A |
| Max. Instantaneous Forward Current at 2.0 A | VF | 0 95 | 1 3 | 1 5 | v |
| Reverse recovery time | Trr | 35 | 50 | nS |
| Max. DC ReverseCurrent at Rated DC Blocking Voltage Ta=25 C Ta=ioo'c | IR | 5.0 100 | uA |
| Max. Thermal Resistance(Note l) | RJL | 20 | c/\N |
| Operating Junction Temperature | Tj | -55 to +150 | C |
| Storage Temperature | TSTG | -55 to +150 | C |
| | | | | | | |
Life support applications - These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
