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PAL18X1A Datasheet

The DS18820-PAR uses Dallas' exclusive l-Wire bus protocol that implements bus communication using one control signal. The control line requires a weak pullup resistor since all devices are linked to the bus via a 3-state or open-drain port (the DQ pin in the case of the DS18820-PAR). In this bus system, the microprocessor (the master device) identifies and addresses devices on the bus using each device's unique 64-bit code. Because each device has a unique code, the number of devices that can be addressed on one bus is virtually unlimited. The l-Wire bus protocol, including detailed explanations of the commands and "time slots," is covered in the l-WIRE BUS SYSTEM section of this datasheet.
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Note * - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
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DESCRIPTION The 704-15K36 & 704-15K36T series of transient voltage suppression modules are for use primarily in avionics equipment. This series meets all applicable enviromental requirements of MIL-S-19500. The sub- assemblies are metallurgically bonded and packaged in a hermetically sealed package. The hermetically sealed package provides high reliability in harsh environmental conditions. In addition, the subassemblies can be 100% TX screened per MIL-S-19500/516 0r/507. Although this series has been designed for 28 voltt aircraft applications, different voltages may be special ordered for specific applications. TVS modules are most often used in applications where discrete TVS diodes do not have high enough surge handling capabality to suppress large power surges.

cs	OE	WE	LB	UB	l/01~8	l/09~16	Mode	Power
H	x	x	x	x	High-Z	High-Z	Deselected	Standby
L	H	H	x	x	High-Z	High-Z	Output Disabled	Active
L	x	x	H	H	High-Z	High-Z	Output Disabled	Active
L	L	H	L	H	Dout	High-Z	Lower Byte Read	Active
L	L	H	H	L	High-Z	Dout	Upper Byte Read	Active
L	L	H	L	L	Dout	Dout	Word Read	Active
L	x	L	L	H	Din	High-Z	Lower Byte Write	Active
L	x	L	H	L	High-Z	Din	Upper Byte Write	Active
L	x	L	L	L	Din	Din	Word Write	Active

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