| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
|
PAL18X6ANM Datasheet Key Features . 200MHz Clock, 400Mbps data rate. . VDD= +2.6V + O.10V, VDDQ= +2.6V + O.10V . Double-data-rate architecture; two data transfers per clock cycle . Bidirectional data strobe(DQS) . Four banks operation . Differential clock inputs(CK and CK) . DLL aligns DQ and DQS transition with CK transition . MRS cycle with address key programs -. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333 -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) . All inputs except data & DM are sampled at the positive going edge of the system clock(CK) . Data l/0 transactions on both edges of data strobe . Edge aligned data output, center aligned data input . LDM,UDM for write masking only (x16) . Auto & Self refresh . 7.8us refresh interval(8K/64ms refresh) . Maximum burst refresh cycle : 8 . 66pin TSOP lI package PAL18X6ANM on stock
The K4S641632C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock l/0 transactions are possible on every clock cycle. Range of operating frequencies, programma- ble burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications. |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
