ESD Protection With RaiIClamps RailOamps are optimized for ESD protection using the rail-to-rail topology. Along with good board layout, these devices virtually eliminate the disadvantages of using discrete components to implement this topology. Consider the situation shown in Figure l where dis- crete diodes or diode arrays are configured for rail-to- rail protection on a high speed line. During positive duration ESD events, the top diode will be forward biased when the voltage on the protected line exceeds the reference voltage plus the VF drop of the diode.
PAL20P6M Price|
| PACKAGING INFORMATION | 1. CATHODE 2. GATE 3. ANODE ~ o*A. SEATING PLANf /M'N .,OO 0:E W ~E OAO~. | SCR TRIAC 1. CATHODE l. MT 1 2. GATE 2. GATE 3. ANODE 3. MT 2 1- 210 170 r $EATINq .600 PLANE lr_o o o .1 .o o .o~o |
| T0-18 (PLASTIC) | T0-92 |
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PAL20P6M on stock| Rank | Q | P |
| hFE2 | 2 000t0 5 000 | 4 000 t0 10 000 |
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| DC Electrical Specifications (Continued) |
| | | | TEST CONDITIONS | vcC | 250C | .400C T0 85aC | .55aC T0 1250C | | |
| PARAMETER | SYMBOL | vI (V) | lo (mA) | (v) | MIN | TYP | MAX | MIN | MAX | MIN | MAX | UNITS |
| Quiescent Device Current | lcc | Vcc or GND | 0 | 6 | | | 8 | | 80 | | 160 | o:A |
| HCT TYPES |
| High Level Input Voltage | VIH | | | 4.5 to 5 5 | 2 | | | 2 | | 2 | | V |
| Low Level Input Voltage | VIL | | | 4.5 to 5 5 | | | 0.8 | | 0.8 | | 0.8 | V |
| High Level Output Voltage CMOS Loads | VOH | VIH or VIL | -0.02 | 4 5 | 4.4 | | | 4 4 | | 4 4 | | V |
| High Level Output Voltage TTL Loads | 4 | 4 5 | 3.98 | | | 3 84 | | 3 7 | | V |
| Low Level Output Voltage CMOS Loads | VOL | VIH or VIL | 0 02 | 4 5 | | | 0.1 | | 0.1 | | 0.1 | V |
| Low Level Output Voltage TTL Loads | 4 | 4 5 | | | 0.26 | | 0 33 | | 0.4 | V |
| Input Leakage Current | JI | Vcc and GND | O | 5 5 | | | +0 1 | | +1 | | ±1 | o:A |
| Quiescent Device Current | lcc | Vcc or GND | 0 | 5 5 | | | 8 | | 80 | | 160 | o:A |
| Additional Quiescent Device Current Per Input Pin: 1 Unit Load | C:lcc (Note 5) | Vcc -2.1 | | 4.5 to 5 5 | | 100 | 360 | | 450 | | 490 | o:A |
| NOTE: 5. For dual-supply systems theoretical worst case (VI = 2.4V, Vcc = 5.5V) specification is l.8mA. HCT Input Loading Table |
| | INPUT | UNIT LOADS | |
| PO - P3 | 0 25 |
| PE | 0 65 |
| CP | 1 05 |
| MR | 0.8 |
| SPE | O5 |
| TE | 1 05 |
| NOTE: Unit Load is Clcc limit specified in DC Electrical Table, e.g., 360ccA max at 250C. |
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