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PAL20R4-15CNL Datasheet

The S3C2400 was developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive applications. Also S3C2400 adopts a new bus architecture, AMBA (Advanced Microcontroller Bus Architecture)
PAL20R4-15CNL Price

Input		Output
×OE	×DIR	Output
L	L	Bus B data output to bus A
L	H	Bus A data output to bus B
H	l	High-impedance state.

PAL20R4-15CNL on stock

Parameter	Symbol	Conditions	Min	Typ.	Max	Unit
Output Voltage	Vout	lo=lOmA, Tj=25IC	3.27	3.3	3.33	V
Output Voltage	Vout	Vin = 4.8V t0 12V lo = 10mA t0 800mA Tj = -25IC t0 125IC	3.23	3.3	3.37	V
Line Regulation	Rline	Vin=4.8V t0 12V, lo=lOmA		1	10	mV
Load Regulation	Rload	lo = 10mA t0 800mA		1	20	mV
Ripple Rejection	RR	f=120Hz, 10=500mA Vin = 6.3 +1- 1Vrms	55			dB
Dropout Voltage	Vdrop	lo = 100mA lo = 500mA lo = 800mA		1 1.05 1.1	1.2 1.25 1.4	V
Quiescent Current	Iq	Vin<=12V		5	10	mA
Temperature Coefficient of Output Voltage	Vo/T	Tj = -25IC t0 125IC lo = 10mA		0.2		mV/IC
Peak Output Current	lpk	Vin=6.3V	800			mA
Output Noise Voltage	Vn	f = 10Hz t0 10KHz		100		VrmS

GENERAL DESCRIPTION The K4S641633H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock and l/0 transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high per- formance memory system applications.

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