| REGISTER | BIT NO | BIT NAME(S) | DEFAULT | DESCRIPTION |
| Setup | O | EN | 1 | 0 = complete power down, 1 = fully active. |
| Register 1 | 1 | CDS | 1 | Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. |
| 54 | PGAFS[1:0] | 00 | Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 00 = Zero output 10 = Full-scale positive output (use for bipolar video) (use for negative going video) 01 = Zero output 11 = Full-scale negative output (use for positive going video) |
| 6 | MODE3 | 0 | Required when operating in MODE3: O = other modes, 1 = MODE3. |
| Setup Register 2 | 2 | INVOP | 0 | Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data. |
| 3 | VRLCEXT | O | When set powers down the RLCDAC, changing its output to Hi-Z, allowing VRLCNBIAS to be externally driven. |
| 5 | RLCDACRNG | 1 | Sets the output range of the RLCDAC. 0 = RLCDAC ranges from O to VDD (approximately), 1 = RLCDAC ranges from O to VRT (approximately). |
| 76 | DEL[1:0] | 00 | Sets the output latency in ADC clock periods. 1 ADC clock period = 2 MCLK periods except in Mode 2 where l ADC clock period = 3 MCLK periods. 00 = Minimum latency 10 = Delay by two ADC clock periods 01 = Delay by one ADC clock 11 = Delay by three ADC clock period periods |
| Setup Register 3 | 30 | RLCV[3:0] | 1111 | Controls RLCDAC driving VRLC pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. |
| 54 | CDSREF[1:0] | 01 | CDS mode reset timing adjust. 00 = Advance l MCLK period 10 = Retard l MCLK period 01 = Normal 11 = Retard 2 MCLK periods |
| Software Reset | | | | Any write to Software Reset causes all cells to be reset. It is recommended that a software reset be performed after a power-up before any other register writes. |
| Setup Register 4 | 3 | RLCINT | O | This bit is used to determine whether Reset Level Clamping is enabled. 0 = RLC disabled, 1 = RLC enabled. |
| 54 | INTM[1:0] | 00 | Colour selection bits used in internal modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table l for details. |
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Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. Human body model, 1.5kQ in series with 100pF. Machine model, 20Qin series with 100pF. 0.8kV between the pairs of +INA, -INA and +INB pins only. 2kV between supply pins, OUTA or OUTB pins and any input pin. +100mA applied to input and output pins to force the device to go into "Iatch-up". The device passes this test to JEDEC spec 17. Positive and Negative supply transient testing increases the supplies by 20% for 100ms.
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| | T | = 150 | oc J | | | | |
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| | | l J | | | Tj | =250C | | |
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| | | l I | | | | | |
| | 1 | l | | | | | |
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