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PALC16R825WC Datasheet

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PALC16R825WC Price

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Gain-Bandwidth Product GBWP 5 MHz
Full-Power Bandwidth FPBW VOUT = 4Vp-p, VCC = 5V 260 kHz
Slew Rate SR 2 V/IJs
Phase Margin PM 68 degrees
Gain Margin GM 21 dB
Total Harmonic Distortion THD f = 10kHz, VOUT = 2Vp-p, AVCL = +1VN 0.005 %
Settling Time t0 0.01% tS AVCL = +1VN, 2V step 2.1 LJs
Input Capacitance CIN 3 pF
Input Voltage Noise Density en f= 1kHz 26 nV/b~z
Input Current Noise Density ln f= 1kHz 0 4 pA/(J'1z
Channel-to-Channel Isolation f = 1kHz, RL = 100kl (MAX4167-MAX4169) 125 dB
Capacitive Load Stability AVCL = +1VN, no sustained oscillations 250 pF
Shutdown Time iSHDN 1 US
Enable Time from Shutdown tENABLE 1 LJs
Power-Up Time tON 5 l_ls


PALC16R825WC on stock

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KIE - Kickstart Enable Interrupt Bit (OFH bit 2) The KIE bit allows the KSF Flag to assert an interrupt. When the KSF flag bit is set to a "1", if KIE is a "1", the IRQF flag bit will be set to a "1". Writing a "0" to the KIE bit will prevent the KSF flag from setting the IRQF flag. This bit is automatically cleared to a logic "0" to by the internal Power on Reset when power is applied and Vcc rises above the Power-fail Voltage.