| Pin | Name | Input Function |
| CLK | System clock | Active on the positive qoinq edqe to sample all inputs. |
| CS | Chip select | Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM |
| CKE | Clock enable | Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. |
| AoA12 | Address | Row/column addresses are multiplexed on the same pins. Row address : RAo ~ RA12, Column address : CAo ~ CA9,CA11 |
| BAoBAi | Bank select address | Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. |
| RAS | Row address strobe | Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. |
| CAS | Column address strobe | Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. |
| WE | Write enable | Enables write operation and row precharge. Latches data in starting from CAS, WE active. |
| DQM | Data input/output mask | Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. |
| DQo3 | Data input/output | Data inputs/outputs are multiplexed on the same pins. |
| VDDNss | Power supply/qround | Power and qround for the input buffers and the core loqic. |
| VDDoNsso | Data output power/ground | Isolated power supply and ground for the output buffers to provide improved noise immunity. |
| N.C/RFU | No connection /reserved for future use | This pin is recommended to be left No Connection on the device. |
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