| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| PAN11016 | CMD | 95 | New&Original | 1128 |
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PAN11016 Datasheet A circuit that suppresses cross-coupling from key to key by water films is shown in Figure 2-2. This circuit includes a 22V10 type CMOS PLD configured with an RC timing circuit to shorten the dwell time of the Y gate pulses. This has the effect of curtailing the charge collected from parts of a water film that are distant from the key, thus reducing the occurrence of cross-coupling among keys when the panel is wet. Rt and Ct are adjusted to provide a timing delay of from 75ns t0 100ns. This circuit is employed in Quantum's E6S2 eval board (Section 5). The 22V10 creates a short delay from the rising edge of the X line in use; this delayed signal is gated with the Y lines to create new, foreshortened Y-gate signals (Figure 2-3). PAN11016 Price M M 5 4 C 9 2 2 / M M 7 4 C 9 2 2 1 6 - K e y E n c o d e r , M M 5 4 C 9 2 3 / M M 7 4 C 9 2 3 2 0 - K e y E n c o d e r PAN11016 on stock Figure l shows a typical application circuit. The regulator is enabled any time the shutdown input is at or above VIH.And shutdown (disabled) when SHDN is at or below VIL. SHDN maybe controlled by a CMOS logic gate, or I/O port of a micro controller. If the SHDN input is not. Required, it should be connected directly to the supply. While in shutdown, supply current decreases t0 0.05UA (typical) and Vout falls to zero volts. NOTES IGuaranteed but not tested. 2DDLO hysteresis is dependent on DDLO threshold value. If DDLO threshold is at maximum, DDLO hysteresis is at maximum at the same time. 3This includes the total reverse current from battery to BVS, BASE, ISENSE, and ADAPTER pins with no adapter present. No signal path between ADAPTER pin and ADPSUPPLY pin. Specifications subject to change without notice. |
