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Q62702-D111-V2 Datasheet

COMMON SOITRCE
Te= = 250(
oGS=4 V
l -10


Q62702-D111-V2 Price

Parameter Symbol Min Max Units
Input capacitance [AO ~ A12] CIN1 5 pF
Input capacitance [RAS, CAS , W, OE] CIN2 7 pF
Output capacitance [DQO - DQ7] CD0 7 pF


Q62702-D111-V2 on stock
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. lfany blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 5. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

Device Code Connector Pin 10 Requirements Comcode
1340FMPC FC-PC No 108162322
1340CMPC SC Internal 1 08354408
1340TMPC ST Connection 1 08572264
1340FAPC FC-PC Requires +5 V or -5 V 1 08468687
1340CAPC SC (Used for photocurrent 108359175
1340TAPC ST monitoring) 1 08572249