| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
Q62702-P1805 Datasheet
Q62702-P1805 Price . HIGH DENSITY PROGRAMMABLE LOGIC - 6000 PLD Gates - 64 110 Pins, Eight Dedicated Inputs - 192 Registers - High Speed Globallnterconnect - Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. - Small Logic Block Size for Random Logic * HIGH PERFORMANCE E2CMOS~ TECHNOLOGY - fmax = 125 MHz Maximum Operating Frequency - tpd = 7.5 ns Propagation Delay - TTL Compatible Inputs and Outputs - Electrically Erasable and Reprogrammable - Non-Volatile 100% Tested at Time of Manufacture - Unused Product Term Shutdown Saves Power Q62702-P1805 on stock The oscillator frequency is divided by 4 prior to clocking the internal decade counters. The three-phase measure- ment cycle takes a total of 4000 counts or 16000 clock pulses. The 4000 count cycle is independent of input signal magnitude. Each phase ofthe measu rement cycle has the following length: Although many semiconductor memories have separate input and output pins, it is possible to design the error detection and correction function using a single EDAC. EDAC data and check bit pins function as inputs or outputs dependent upon the state of control signals SO and Sl. It becomes necessary to use wired AND logic, with fairly complex timing system, to control the EDAC and data bus. This scheme becomes difficult to implement both in terms of board layout and timing. System performance is also adversely affected, See Figure 2. Optimised systems can be implemented using two EDAC's in parallel, One of the units is used strictly as an encoder during the memory write cycle. Both controls SO and Sl are |
