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Q62702-P9 Datasheet

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TERMINAL
NAME NO.		TYPE	DESCRIPTION
SIGNAL PIN (CONTINUED)
SYNC 25		Input (w/pulldown)	Fast synchronization. When asserted high, the transmitter substitutes the 18-bit pattern 111111111000000000, so that when the start/stop bits are framed around the data the receiver can immediately detect the proper deserialization boundary. This is typically used during initialization of the serial link.
PREEMPH 56		Input	Preemphasis. When asserted, the serial transmit outputs have an extra output swing on the first bit of any run-length of same value bits. If the run-length of output bits is one, then that bit has a larger output swing.
TEST PIN
ENABLE	24	Input (w/pullup)	Device enable. When this pin is held low, the device is placed in power down mode. When asserted high while the device is in power-down mode, the transceiver goes into power-on reset before beginning normal operation.
LOOPEN	21	Input (w/pulldown)	Loop enable. When LOOPEN is active high, the internal loop-back path is activated. The transmitted serial data is directly routed internally to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The DOUTTXP and DOUTTXN outputs are held in a high-impedance state during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active.
LOCKB	26	Output	Receiver lock. When asserted low, it indicates that the receiver has acquired bit synchronization on the data stream and has located the start/stop bits, so that the deserialized data presented on the parallel receive bus is properly received.
TESTEN	27	Input (w/pulldown)	Test mode enable. This pin should be left unconnected or tied low.
POWER PIN
VDD	1 9 23,38 48	Supply	Digital logic power. Provides power for all digital circuitry and digital l/0 buffers.
VDDA	55 57	Supply	Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver and transmitter.
GROUND PIN
GNDA	52,58 61	Ground	Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and TX.
GND	5, 13, 18, 28, 33, 43	Ground	Digital logic ground. Provides a ground for the logic circuits and digital l/0 buffers.

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OUTLINE The RN5RKxxlA/xxlB/xx2A Series are VFM (Chopper) Step-up DC/DC converter ICs with ultra low supply cur- rent and high output voltage accuracy by CMOS process. Each of the RN5RKxxlA/xxlB consists of an oscillator, a VFM control circuit, a driver transistor to have low ON resistance (Lx switch), a reference voltage unit, a high speed comparator, resistors for voltage detection, an Lx switch protection circuit and an internal chip enable circuit. A low ripple, high efficiency step-up DC/DC converter can be composed of this RN5RKxxlA/xxlB with only three external components: an inductor, a diode and a capacitor. The RN5RKxx2A uses the same chip as what is employed in the RN5RKxxlA/lB IC and has a drive pin (EXT) for an external transistor instead of an Lx pin. As it is possible to load a large output current with a power transistor which has a low saturation voltage, RN5RKxx2A IC is recommendable to users who need an output current as large as between several tens mA and several hundreds mA. Using the chip enable function, it is possible to make the supply current on standby minimized. Since the package for these ICs are SOT-23-5 (Mini-mold), high density mounting of the ICs on board is possible.

After writing the first set of data up t0 2112 byte into the selected page register, Dummy Page Program command (11h) instead of actual Page Program command (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (70h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(l/0 6). Then the next set of data for the other plane is inputted after the 81h command and address sequences. After inputting data for the last plane, actual True Page Program(lOh) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Althougth two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of 110 0 is set to "1" when any of the pages fails. Restriction in addressing with Two-Plane Page Program is shown is Figure14.

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