Q62703-Q6103 Datasheet ISANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein. Q62703-Q6103 Price| Freq. (MHz) | Opt | Angle | Fmin (dB) | R noise | | 1800 | 0.453 | 95.8 | 1.476 | 14.2 | | 1960 | 0.459 | 109.4 | 1.178 | 9.58 | | 2040 | 0.437 | 116.4 | 1.287 | 8.17 | | | | | |
Q62703-Q6103 on stock| OB rise | OB High Time Constant | Pin 38, OB 0 t0 1 | 4 | | | m V/ocs | | OB_decay | OB Low Time Constant | Pin 38, OB l t0 0 | | | 2 | mV/ms | | BLK RAN | Black Level Adjust Range | Pins 8 t0 15, OB high, Serial bus from HOO to HIF | | 31 | | LSBs | | BLK res | Black Level Adjust Resolution | Pins8t015,perserialbusLSBstep | | 1 | | LSBs | | BLK LEV | Black Level Adjust | Pins 8 t0 15 Bus = HOO Bus = HIF | 29 | 0 31 | 2 33 | LSBs LSBs | | ADC DN | ADC Input Dynamic Range (output from o t0 255) | Pin 38 test signal above black clamping level (VBOT) | 1.4 | 1.55 | 1.7 | VPP | | fCLK | ADC Clock Frequency | Pin 24 | | 12 | | MHz | | tPCLK | Output Pipeline Delay (3) | From a sampling to data out | 3 | | 3 | CLK cycles | | tDADC | Clock to Data Out (4) | CLK positive edge, CLOAD = 20pF | | 17 | | ns | | RLADD | Ladder Resistance | Between Pins 36 and 37 | | 330 | | | | VTOP | Top Reference Voltage | Pin 36 | 32 | 3.35 | 3.5 | V | | VBOT | Bottom Reference Voltage | Pin 37 | 1.71 | 1.8 | 1.89 | V | | ADC lin | ADC Linearity | Data out, input signal between [VBOT + 25mV ; VTOP - 25mV] | | | 1 | % | | | | | | | |
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