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Q67000-A8187 Datasheet Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. Q67000-A8187 Price . 1.8 + 0.1 V power supply and HSTL l/0 . DLL circuitry for wide output data valid window and future frequency scaling . Separate independent read and write data ports with concurrent transactions . 100% bus utilization DDR READ and WRITE operation . Four-tick burst for reduced address frequency * Two input clocks (K and /K) for precise DDR timing at clock rising edges only * Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device . Internally self-timed write control * Clock-stop capability with ps restart . User programmable impedance output . Fast clock cycle time : 3.3 ns (300 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz) . Simple control logic for easy depth expansion . JTAG boundary scan Q67000-A8187 on stock
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