| PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS |
| vcc to Reset Output Delay | tRD | Vccl = (VTHl+lOOmV) to (VTHl - 100mV) or VCC2 = (VTH2 + 75mV) to (VTH2 - 75mV) | 20 | US |
| | | D1 | 1 1 1 65 2 2 | |
| D2 | 8 8 13 2 17 6 |
| D3 | 140 210 280 |
| Reset Timeout Period | tRP | D5 | 280 420 560 | ms |
| D6 | 560 840 1120 |
| D4 | 1120 1680 2240 |
| ADJUSTABLE RESET COMPARATOR INPUT (MAX6719/MAX6720/MAX6723-MAX6727) |
| RSTIN Input Threshold | VRSTIN | | 611 626 5 642 | mV |
| RSTIN Input Current | IRSTllxl | | -25 +25 | nA |
| RSTIN Hysteresis | | | 3 | mV |
| RSTIN to Reset Output Delay | tRSTIKID | VRSTIKI to (VRSTIN - 30mV) | 22 | US |
| POWER-FAIL INPUT (MAX6728/MAX6729) |
| PFI Input Threshold | VPFI | | 611 626 5 642 | mV |
| PFI Input Current | IPFI | | -25 +25 | nA |
| PFI Hysteresis | VPFH | | 3 | mV |
| PFI to PFO Delay | tDPF | (VPFI + 30mV) to (VPFI - 30mV) | 2 | US |
| MANUAL RESET INPUT (MAX67' | 5-MAX6722/MAX6725-MAX6729) |
| | VIL | | 0 3×Vccl | |
| MR Input Voltage | VIH | | 0 7×VCC1 | V |
| MR Minimum Pulse Width | | | 1 | US |
| MR Glitch Rejection | | | 100 | ns |
| MR to Reset Delay | tMR | | 200 | ns |
| MR Pullup Resistance | | | 25 50 80 | kQ |
| WATCHDOG INPUT (MAX6721-MAX6729) |
| Watchdog Timeout Period | tWD | First watchdog period after reset timeout period | 35 54 72 | S |
| Normal mode | 1 12 1 68 2 24 |
| WDI Pulse Width | tWDI | (lxlote 21 | 50 | ns |
| | VIL | | 0 3×VCC1 | |
| WDI Input Voltage | VIH | 0 7×VCC1 | V |
| WDI Input Current | IWDI | WDI = 0 0r VCC1 | 1+1 | UA |
| | | | |
