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QD27256L-1 Datasheet

interface for monitor identification, including recovery to DDC1 Pin and function compatible with 24LC21 Low power CMOS technology - 1 mA typical active current - 10 0A standby current typical at 5.5V 2-wire serial interface bus, 12CTM compatible 100 kHz (2.5V) and 400 kHz (5V) compatibility Self-timed write cycle (including auto-erase) Page-write buffer for up to eight bytes 1,000,000 erase/write cycles guaranteed Data retention > 200 years ESD Protection > 4000V 8-pin PDIP and SOIC package Available for extended temperature ranges - CommerciaI(C): OoC to +700C - Industrial (1): -400C to +85aC
QD27256L-1 Price

Product number	FDr use with 1ube OD/1D	B	C	D	E lVF
242260618	6/4	18	7 5	23 3	14
242260628	6/4		11 0	27 0	17
242260638	6/4	38	11 5	28 0	22
242260818	8/6	18	7 5	24 7	14
242260828	8/6		11 0	28 7	17
242260838	8/6	38	11 5	292	22
242260848	8/6	12	15 0	33 0	24
242261028	10/8		11 0	30 5	17
242261038	10/8	38	11 5	33 3	22
242261048	10/8	12	150	34 5	24

QD27256L-1 on stock

lnformation (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

Parameter	Min Max Unit	Comments
MASTER CLOCK AND RESET tMH MCLK High tML MCLK Low tPDR PD/RST Low	15 ns 15 ns 20 ns
SPI PORT tCCH CCLK High tCCL CCLK Low tCCP CCLK Period tCDS CDATA Setup tCDH CDATA Hold tcLs CLATCH Setup tCLH CLATCH Hold tCOE COUT Enable tCOD COUT Delay tCOT5 COUT Three-State	40 ns 40 ns 80 ns 10 ns 10 ns 10 ns 10 ns 15 ns 20 ns 25 ns	To CCLK rising edge From CCLK rising edge To CCLK rising edge From CCLK rising edge From CLATCH falling edge From CCLK falling edge From CLATCH rising edge
DAC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Slave) tDBH DBCLK High tDBL DBCLK Low fDB DBCLK Frequency tDLS DLRCLK Setup tDLH DLRCLK Hold tDDS DSDATA Setup tDDH DSDATA Hold Packed 128/256 Modes (Slave) tDBH DBCLK High tDBL DBCLK Low fDB DBCLK Frequency tDLS DLRCLK Setup tDLH DLRCLK Hold tDDS DSDATA Setup tDDH DSDATA Hold	60 ns 60 ns 64 x fs 10 ns 10 ns 10 ns 10 ns 15 ns 15 ns 256 x fs 10 ns 10 ns 10 ns 10 ns	To DBCLK rising edge From DBCLK rising edge To DBCLK rising edge From DBCLK rising edge To DBCLK rising edge From DBCLK rising edge To DBCLK rising edge From DBCLK rising edge
ADC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Master) tABD ABCLK Delay tALD ALRCLK Delay tABDD ASDATA Delay Normal Mode (Slave) tABH ABCLK High tABL ABCLK Low fAB ABCLK Frequency tALS ALRCLK Setup tALH ALRCLK Hold tABDD ASDATA Delay Packed 128/256 Mode (Master) tPABD ABCLK Delay tPALD LRCLK Delay tPABDD ASDATA Delay	25 ns 5 ns 10 ns 60 ns 60 ns 64 x fs 5 ns 15 ns 15 ns 40 ns 5 ns 10 ns	From MCLK rising edge From ABCLK falling edge From ABCLK falling edge To ABCLK rising edge From ABCLK rising edge From ABCLK falling edge From MCLK rising edge From ABCLK falling edge From ABCLK falling edge

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