| KA5x0280R |
| Drain-Gate Voltage (RGS=1M I | VDGR | 800 | V |
| Gate-Source (GND) Voltage | VGS | +30 | V |
| Drain Current Pulsed (1) | IDM | 8.0 | ADC |
| Continuous Drain Current (TC=25IC) | ID | 2.0 | ADC |
| Continuous Drain Current (TC=100IC) | ID | 1.3 | ADC |
| Single Pulsed Avalanche Energy (2) | EAS | 90 | mJ |
| Maximum Supply Voltage | VCC,MAX | 30 | V |
| Analog Input Voltage Range | VFB | -0.3 to VSD | V |
| | PD | 35 | W |
| Total Power Dissipation | Darting | 0.28 | W/IC |
| Operating Junction Temperature. | Tj | +160 | ][C |
| Operating Ambient Temperature. | | -25 to +85 | ][C |
| Storage Temperature Range. | TSTG | -55 to +150 | IC |
| | | |
| | G= +2 | | | | | | |
| | | Dlo | Bandwi | dth= | 682MH | '7 | -- | ~ l |
| | | | | | | | | |
| | | | s | 0-8 B | | h= 68 | 0MHz | |
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QEX2E104KTPT on stock I FEATURES 0 11 Bands Each for Left and Rjght Channels O Stereo Application Graphic Equalizer Each Channel Independent Operation O Maximum Boost and Cut +12dB O Boost and Cut Step +2dB 0 10bit Serial Data for the Equalizirig O Flat Level Setting Function O Operating Voltage 15V 30V O Package Outline SDlP 42/SOP 40 O C-MOS Technology
