QF62A1 Datasheet| SYMBOL | PARAMETER | CONDITIONS | TYPICAL | UNIT | | tPHL/tPLH | Propagation delay An to Yn | CL = 50pF Vcc = 3.3V | 3.9 | ns | | fmax | Maximum clock frequency | 250 | MHz | | Cl | Input capacitance | | 5.0 | pF | | Cl/0 | Input/output capacitance | | 10 | pF | | CPD | Power dissipation capacitance per gate | Notes l.2 | 26 | pF | | | | | |
QF62A1 Price| CHARACTERISTIC | SYMBOL | MIN | TYP | MAX | UNIT | TEST CONDITIONS | | Collector Cutoff Current | ICBO | | | -100 | | VCB = -400 V, IE = 0 | | Emitter Cutoff Current | IEBO | | | -10 | | VEB = -5.0 V. Ic = O | | DC Current Gain | hFE* | 30 | | 200 | | VCE = -5.0 V, lc = -50 mA | | Collector Saturation Voltage | VCEtsatl* | | | -1.0 | V | lc = -100 rriA. lB = -10 fTiA | | Base Saturation Voltage | VBE(satl* | | | -1.2 | V | lc = -100 FriA, lB = -10 ffiA | | Turn-on Time | ton | | | 1.0 | us | lc = -100 mA, RL - 1.5 kQ | | Storage Time | tstg | | | 5.0 | | lai = -182 = -10 mA, | | Fall time | tf | | | 1.0 | S | Vcc -. -150 V PW < 50 ps, Duty Cycle < 2 % | | | | | | | |
QF62A1 on stock| 1U Kl2 | jX | | V | ^ 10 kQ | j | | | vvv | | | | +15V 15V 10 kQ | | j- | | | | 100 kQ AAA | | | | 1MQ AAA | | VVv | | | 0 | vvv | | Ai O- | >- | < | Binary --o Ao Input | Gain | | y DG304B | 11 | 1 | | 10 00 | 10 100 1000 | | | | | | | | | | | | |
input. On the rising edge of CONVST, all four on-chip track/ holds are simultaneously placed into hold and the conversion sequence is started on all the selected channels. Channel selec- tion is made via the SLl-SL4 pins if HIS SEL is logic zero, or via the channel select register if H/S SEL is logic one-see Selecting a Conversion Sequence. The channel select register is programmed via the bidirectional data lines DBO-DB3 and a standard write operation. The selected conversion sequence is
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