| Symbol | Pin Number | Type | . Description |
| CLB# | 78 | l | The CLB# input is asynchronous and active low, and clears the CAS 1993. When CLB# goes low, the circuit immediately enters its RESET mode and normal operation will resume 3 XIN rising edges later after CLB# returned high. The 12C register contents are all initialized to their default values. The minimum width of CLB# at low level is 3 XIN clock periods. |
| XIN | 97 | l | Crystal oscillator input pin. Typically a fundamental XTAL oscillator is connected between the XIN and XOUT pins. (See typical application ). |
| XOUT | 96 | O | Crystal oscillator output pin. Typically a fundamental XTAL oscillator is connected between the XIN and XOUT pins. (See typical application .) |
| SACLK | 3 | O | SamplingCLocK output. SACLK is nominally a square wave clock with a maximum of 93 MHz depending on the XTAL connected between XIN and XOUT and the multiplying factor of the PLL. SACLK is provided in case an external A/D is used only. When the internal A/D is used, SACLK is set t0 0. |
| PLLAVS | 99 | l | Analog ground for the PLL. |
| PLLAVD | 1 00 | l | Analog positive supply voltage for the PLL. PLLAVD is typically 3.3V. |
| And | 6,7,8,9,10,11 16,17,18,19,20, 21 | l l | 1[5:0] and Q[5:0] are the 6-bit in-phase and quadrature base-band symbol input signals respectively, coming from an external dual A/D converter. These signals are sampled on the rising edge of SACLK. The input data may be in either offset binary (default) or two's complement format.(See ).When not used, these 12 pins must be grounded (use of the internal ADCs). |
| VAGC | 5 | O 5V | PWM encoded output signal for AGC. This signal is typically fed to the AGC amplifier through a single RC network (see typical application ' ). The maximum signal frequency on VAGC output is SACLK / 8. The refresh frequency of AGC information is the symbol rate divided by 2048. |
| CTRL1 | 4 | O 5V | ConTRoL line output. This output is directly programmable through the 12C interface. Its default value is a logical "1". CTRLl is an open drain output and therefore requires an external pull- up resistor to either VDD or VCC. |
| CTRL2 | 27 | O 5V | ConTRoL line output. This output is directly programmable through the 12C interface. Its default value is a logical "0". CTRL2 is an open drain output and therefore requires an external pull-up resistor to either VDD or VCC. |
| CTRL3 | 92 | O 5V | ConTRoL Line output. This output is directly programmable through the 12C interface. Its default value is a logical "0". CTRL3 is an open drain output and therefore requires an external pull-up resistor to either VDD or VCC. |
| CTRL4 | 87 | I/O 5V | ConTRoL Line input/output. This pin is directly programmable through the 12C interface. Its default configuration is an input. A pull-up to VDD or VCC, or a pull-down resistor to VSS must be connected to CTRL4. |
| D0[7:0] | 56,57,58, 60,64,65, 67,68 | O 3.3V | Data Output bus . These 8-bit parallel data are the outputs of the VES 1993 after demodulation, Viterbi decoding, de-interleaving, RS decoding and de-scrambling. There are 3 possible output interfaces : two parallel and one serial (See |
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