The W530-02 uses a PLL to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 7. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This
| TYPE | ZENER VOLTAGE Vz(V) @lzt(mA) | MAX ZENER IMPEDANCE Rz (ohms) @lzt(mA) | MAX ZENER IMPEDANCE Rz(ohms) @Izl(mA) | MAXIMUM REVERSE CURRENT @VR (V) IR (uA) | TEMP. COEFF. dvz |
| 1N4728A | 3.3 76 | 10.0 76 | 400 1.0 | 1.0 100 | -0.06 |
| 1N4729A | 3.6 69 | 10.0 69 | 400 1.0 | 1.0 100 | -0.06 |
| 1N4730A | 3.9 64 | 9.0 64 | 400 1.0 | 1.0 50 | -0.05 |
| 1N4731A | 4.3 58 | 9.0 58 | 400 1.0 | 1.0 10 | -0.03 |
| 1N4732A | 4.7 53 | 8.0 53 | 500 1.0 | 1.0 10 | -0.01 |
| 1N4733A | 5.1 49 | 7.0 49 | 550 1.0 | 1.0 10 | 0.01 |
| 1N4734A | 5.6 45 | 5.0 45 | 600 1.0 | 2.0 10 | 0.03 |
| 1N4735A | 6.2 41 | 2.0 41 | 700 1.0 | 3.0 10 | 0.04 |
| 1N4736A | 6.8 37 | 3.5 37 | 700 1.0 | 4.0 1 0 | 0.05 |
| 1N4737A | 7.5 34 | 4.0 34 | 700 0.5 | 5.0 10 | 0.05 |
| 1N4738A | 8.2 31 | 4.5 31 | 700 0.5 | 6.0 10 | 0.06 |
| 1N4739A | 9.1 28 | 5.0 28 | 700 0.5 | 7.0 10 | 0.06 |
| 1N4740A | 10.0 25 | 7.0 25 | 700 0.25 | 7.6 10 | 0.07 |
| | | | | |
